soc/intel/apollolake: Add PrmrrSize and SGX enable config

Add PrmrrSize and sgx_enable config option. PrmrrSize gets
configured in romstage so that FSP can allocate memory for SGX.
Also, adjust cbmem_top() calculation.

Change-Id: I56165ca201163a8b8b522e9aeb47bd1f4267be5e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/soc/intel/apollolake/chip.h

@@ -121,6 +121,18 @@ struct soc_intel_apollolake_config {
 
 	/* GPIO SD card detect pin */
 	unsigned int sdcard_cd_gpio;
+
+	/* PRMRR size setting with three options
+	 *  0x02000000 - 32MiB
+	 *  0x04000000 - 64MiB
+	 *  0x08000000 - 128MiB */
+	uint32_t PrmrrSize;
+
+	/* Enable SGX feature.
+	 * Enabling SGX feature is 2 step process,
+	 * (1) set sgx_enable = 1
+	 * (2) set PrmrrSize to supported size */
+	uint8_t sgx_enable;
 };
 
 typedef struct soc_intel_apollolake_config config_t;

src/soc/intel/apollolake/memmap.c

@@ -26,6 +26,7 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <cbmem.h>
+#include "chip.h"
 #include <device/pci.h>
 #include <fsp/memmap.h>
 #include <intelblocks/smm.h>
@@ -34,7 +35,25 @@
 
 void *cbmem_top(void)
 {
-	return (void *)sa_get_tseg_base();
+	const struct device *dev;
+	const config_t *config;
+	void *tolum = (void *)sa_get_tseg_base();
+
+	if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+		return tolum;
+
+	dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	assert(dev != NULL);
+	config = dev->chip_info;
+
+	if (!config)
+		die("Failed to get chip_info\n");
+
+	/* FSP allocates 2x PRMRR Size Memory for alignment */
+	if (config->sgx_enable)
+		tolum -= config->PrmrrSize * 2;
+
+	return tolum;
 }
 
 int smm_subregion(int sub, void **start, size_t *size)

src/soc/intel/apollolake/romstage.c

@@ -320,6 +320,22 @@ static void check_full_retrain(const FSPM_UPD *mupd)
 	}
 }
 
+static void soc_memory_init_params(FSPM_UPD *mupd)
+{
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	/* Only for GLK */
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	assert(dev != NULL);
+	const config_t *config = dev->chip_info;
+	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+	if (!config)
+		die("Can not find SoC devicetree\n");
+
+	m_cfg->PrmrrSize = config->PrmrrSize;
+#endif
+}
+
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	struct region_device rdev;
@@ -327,6 +343,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	check_full_retrain(mupd);
 
 	fill_console_params(mupd);
+
+	if (IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+		soc_memory_init_params(mupd);
+
 	mainboard_memory_init_params(mupd);
 
 	/* Do NOT let FSP do any GPIO pad configuration */