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mb/google,intel: Add ChromeOS GPIOs to onboard.h

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Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki
2021-11-05 22:02:26 +02:00
parent 4cdac3c7b3
commit 4bcc275d71
18 changed files with 92 additions and 38 deletions
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11
src/mainboard/intel/baskingridge/chromeos.c
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@@ -7,12 +7,13 @@
#include <southbridge/intel/common/gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
{69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
{GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
/* Hard code the lid switch GPIO to open. */
{-1, ACTIVE_HIGH, 1, "lid"},
@@ -32,18 +33,18 @@ int get_recovery_mode_switch(void)
* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
* J8E2. The jump is active high.
*/
return get_gpio(69);
return get_gpio(GPIO_REC_MODE);
}
int get_write_protect_state(void)
{
/* Write protect is active low, so invert it here */
return !get_gpio(22);
return !get_gpio(GPIO_SPI_WP);
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};
void mainboard_chromeos_acpi_generate(void)