From 4bf67af21213dd222744b1ec50e0e69075d7ae3e Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 18 Feb 2020 10:22:15 -0700 Subject: [PATCH] Add LPC decode of new memory map regions to cml-u and whl-u --- src/mainboard/system76/cml-u/devicetree.cb | 12 ++++++------ src/mainboard/system76/whl-u/devicetree.cb | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index cce39187b3..9e511d648f 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -148,14 +148,14 @@ chip soc/intel/cannonlake # LPC (soc/intel/cannonlake/lpc.c) # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x84: Decode 0x80 - 0x8F + # Address 0x84: Decode 0x80 - 0x8F (Port 80) register "gen1_dec" = "0x000c0081" - # Address 0x88: Decode 0x68 - 0x6F + # Address 0x88: Decode 0x68 - 0x6F (PMC) register "gen2_dec" = "0x00040069" - # Address 0x8C: Decode 0x3320 - 0x332F - register "gen3_dec" = "0x000c3321" - # Address 0x90: Disabled - register "gen4_dec" = "0x00000000" + # Address 0x8C: Decode 0xC00 - 0xCFF (AP/EC command) + register "gen3_dec" = "0x00fc0C01" + # Address 0x90: Decode 0xD00 - 0xDFF (AP/EC debug) + register "gen4_dec" = "0x00fc0D01" # PMC (soc/intel/cannonlake/pmc.c) # Enable deep Sx states diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index cce39187b3..9e511d648f 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -148,14 +148,14 @@ chip soc/intel/cannonlake # LPC (soc/intel/cannonlake/lpc.c) # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x84: Decode 0x80 - 0x8F + # Address 0x84: Decode 0x80 - 0x8F (Port 80) register "gen1_dec" = "0x000c0081" - # Address 0x88: Decode 0x68 - 0x6F + # Address 0x88: Decode 0x68 - 0x6F (PMC) register "gen2_dec" = "0x00040069" - # Address 0x8C: Decode 0x3320 - 0x332F - register "gen3_dec" = "0x000c3321" - # Address 0x90: Disabled - register "gen4_dec" = "0x00000000" + # Address 0x8C: Decode 0xC00 - 0xCFF (AP/EC command) + register "gen3_dec" = "0x00fc0C01" + # Address 0x90: Decode 0xD00 - 0xDFF (AP/EC debug) + register "gen4_dec" = "0x00fc0D01" # PMC (soc/intel/cannonlake/pmc.c) # Enable deep Sx states