diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb
index 529767c568..87fdc2a5fe 100644
--- a/src/mainboard/system76/addw1/devicetree.cb
+++ b/src/mainboard/system76/addw1/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 
diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb
index ad70b0595b..05a61a935f 100644
--- a/src/mainboard/system76/adl/devicetree.cb
+++ b/src/mainboard/system76/adl/devicetree.cb
@@ -11,6 +11,10 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 
diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb
index d79aa76659..79a695e030 100644
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 
diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb
index 90c5b719b0..999ca33259 100644
--- a/src/mainboard/system76/cml-u/devicetree.cb
+++ b/src/mainboard/system76/cml-u/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
 	register "enable_c6dram" = "1"
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index 4ae412d155..3b8e666d0e 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 
diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb
index f17862f4af..3db2e0a8b7 100644
--- a/src/mainboard/system76/oryp5/devicetree.cb
+++ b/src/mainboard/system76/oryp5/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index c0c1b4a12a..37971ae80b 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "enable_c6dram" = "1"
 
diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb
index a016dec962..cdfd41e2b3 100644
--- a/src/mainboard/system76/rpl/devicetree.cb
+++ b/src/mainboard/system76/rpl/devicetree.cb
@@ -11,6 +11,10 @@ chip soc/intel/alderlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 	# Enable C6 DRAM
 	register "enable_c6dram" = "1"
 
diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb
index 353a96d329..1038844168 100644
--- a/src/mainboard/system76/tgl-h/devicetree.cb
+++ b/src/mainboard/system76/tgl-h/devicetree.cb
@@ -12,6 +12,10 @@ chip soc/intel/tigerlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # CPU (soc/intel/tigerlake/cpu.c)
 	# Power limits
 	register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb
index 0899f624ec..231ad7a985 100644
--- a/src/mainboard/system76/whl-u/devicetree.cb
+++ b/src/mainboard/system76/whl-u/devicetree.cb
@@ -18,6 +18,10 @@ chip soc/intel/cannonlake
 	# Enable Enhanced Intel SpeedStep
 	register "eist_enable" = "1"
 
+	# Enable S0ix but prefer S3 suspend
+	register "s0ix_enable" = "true"
+	register "prefer_s3_suspend" = "true"
+
 # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
 	register "SaGv" = "SaGv_Enabled"
 	register "enable_c6dram" = "1"