Make AMD Fam10h CPU microcode updates optional in Expert mode

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/amd/model_10xxx/Kconfig

@@ -50,3 +50,35 @@ config SET_FIDVID_CORE_RANGE
 
 endif
 endif
+
+config UPDATE_CPU_MICROCODE
+	bool
+	default y
+
+config UPDATE_CPU_MICROCODE
+	bool "Update CPU microcode"
+	default y
+	depends on EXPERT && CPU_AMD_MODEL_10XXX
+	help
+	  Select this to apply patches to the CPU microcode provided by
+	  AMD without source, and distributed with coreboot, to address
+	  issues in the CPU post production.
+
+	  Microcode updates distributed with coreboot are not necessarily
+	  the latest version available from AMD. Updates are only applied
+	  if they are newer than the microcode already in your CPU.
+
+	  Unselect this to let Fam10h CPUs run with microcode as shipped
+	  from factory. No binary microcode patches will be included in the
+	  coreboot image in that case, which can help with creating an image
+	  for which complete source code is available, which in turn might
+	  simplify license compliance.
+
+	  Microcode updates intend to solve issues that have been discovered
+	  after CPU production. The common case is that systems work as
+	  intended with updated microcode, but we have also seen cases where
+	  issues were solved by not applying the microcode updates.
+
+	  Note that some operating system include these same microcode
+	  patches, so you may need to also disable microcode updates in
+	  your operating system in order for this option to matter.

src/cpu/amd/model_10xxx/Makefile.inc

@@ -1,5 +1,4 @@
-# no conditionals here. If you include this file from a socket, then you get all the binaries.
 driver-y += model_10xxx_init.c
-ramstage-y += update_microcode.c
+ramstage-$(CONFIG_UPDATE_CPU_MICROCODE) += update_microcode.c
 ramstage-y += apic_timer.c
 ramstage-y += processor_name.c

src/cpu/amd/model_10xxx/init_cpus.c

@@ -325,7 +325,9 @@ static u32 init_cpus(u32 cpu_init_detectedx)
 		 * This happens after HTinit.
 		 * The BSP runs this code in it's own path.
 		 */
+#if CONFIG_UPDATE_CPU_MICROCODE
 		update_microcode(cpuid_eax(1));
+#endif
 		cpuSetAMDMSR();
 
 #if CONFIG_SET_FIDVID