cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/3729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Stefan Reinauer
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@@ -39,7 +39,7 @@
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#include "chip.h"
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/*
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* List of suported C-states in this processor
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* List of supported C-states in this processor
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*
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* Latencies are typical worst-case package exit time in uS
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* taken from the SandyBridge BIOS specification.
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@@ -374,7 +374,7 @@ static void configure_thermal_target(void)
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return;
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conf = lapic->chip_info;
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/* Set TCC activaiton offset if supported */
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/* Set TCC activation offset if supported */
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msr = rdmsr(MSR_PLATFORM_INFO);
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if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
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msr = rdmsr(MSR_TEMPERATURE_TARGET);
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