cpu: Fix spelling

Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth
2013-07-08 16:23:54 -06:00
committed by Stefan Reinauer
parent 0cb07e3476
commit 4c3ab7376e
44 changed files with 102 additions and 102 deletions

View File

@@ -39,7 +39,7 @@
#include "chip.h"
/*
* List of suported C-states in this processor
* List of supported C-states in this processor
*
* Latencies are typical worst-case package exit time in uS
* taken from the SandyBridge BIOS specification.
@@ -374,7 +374,7 @@ static void configure_thermal_target(void)
return;
conf = lapic->chip_info;
/* Set TCC activaiton offset if supported */
/* Set TCC activation offset if supported */
msr = rdmsr(MSR_PLATFORM_INFO);
if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
msr = rdmsr(MSR_TEMPERATURE_TARGET);