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mb/google/brya: Deduplicate chipset lockdown config

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Due to an issue in sconfig, move `chipset_lockdown` out of
`common_soc_config` and configure it separately in the baseboard's
devicetree since it might get overwritten if a variant configures
`common_soc_config`.

Also, deduplicate the configuration of `chipset_lockdown`.

Change-Id: Id969346df06aa82ab2ad2b1aa4884a9bcd876d75
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56408
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2021-07-17 05:27:18 +02:00
committed by Nico Huber
parent 32ca3ac9ab
commit 4c426262d7
2 changed files with 1 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brya/variants/baseboard/devicetree.cb
View File

@@ -92,8 +92,8 @@ chip soc/intel/alderlake
#| | for TPM communication |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},

2
src/mainboard/google/brya/variants/primus/overridetree.cb
View File

@@ -27,7 +27,6 @@ chip soc/intel/alderlake
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio |
#| I2C1 | Touchscreen |
@@ -38,7 +37,6 @@ chip soc/intel/alderlake
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},