soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree

Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/google/jecht/devicetree.cb

@@ -12,6 +12,7 @@ chip soc/intel/broadwell
 	register "dq_pins_interleaved" = "true"
 
 	device cpu_cluster 0 on
+		ops broadwell_cpu_bus_ops
 		chip cpu/intel/haswell
 			device lapic 0 on end
 			device lapic 0xacac off end
@@ -19,6 +20,7 @@ chip soc/intel/broadwell
 	end
 
 	device domain 0 on
+		ops broadwell_pci_domain_ops
 		device pci 00.0 on end # host bridge
 		device pci 02.0 on end # vga controller
 		device pci 03.0 on end # mini-hd audio