soc/intel/cmn/cpu: Introduce common CAR APIs

This patch adds `car_lib.c` to the IA common code to consolidate
SoC-agnostic CAR APIs. Initially, it includes `car_report_cache_info()`
to provide a unified way to read cache information, reducing the need
for SoC-specific implementations.

TEST=Builds successfully for google/rex.

Change-Id: I2ff84b27736057d19d4ec68c9afcb9b22e778f55
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>

src/soc/intel/common/block/cpu/Makefile.mk

@@ -12,6 +12,8 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_r
 postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/exit_car.S
 endif
 
+bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/car_lib.c
+
 bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
 romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c

src/soc/intel/common/block/cpu/car/car_lib.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <intelblocks/car_lib.h>
+
+/*
+ * Gathers and prints information about the CPU's L3 cache.
+ *
+ *  This function does the following:
+ *      1. Sets the cache level of interest to L3.
+ *      2. Prints the following cache details to the console:
+ *          - Cache level
+ *          - Associativity (number of ways)
+ *          - Number of physical partitions
+ *          - Line size (in bytes)
+ *          - Number of sets
+ *          - Total cache size (in MiB), calculated using the 'get_cache_size' function.
+ */
+void car_report_cache_info(void)
+{
+	int cache_level = CACHE_L3;
+	struct cpu_cache_info info;
+
+	if (!fill_cpu_cache_info(cache_level, &info))
+		return;
+
+	printk(BIOS_INFO, "Cache: Level %d: ", cache_level);
+	printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n",
+		info.num_ways, info.physical_partitions, info.line_size, info.num_sets);
+
+	printk(BIOS_INFO, "Cache size = %zu MiB\n", get_cache_size(&info)/MiB);
+}

src/soc/intel/common/block/include/intelblocks/car_lib.h

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_CAR_LIB_H
+#define SOC_INTEL_COMMON_BLOCK_CAR_LIB_H
+
+#include <types.h>
+
+/* Gathers and prints information about the CPU's L3 cache */
+void car_report_cache_info(void);
+
+#endif	/* SOC_INTEL_COMMON_BLOCK_CAR_LIB_H */