sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/x4x: Use common code for SMM in TSEG

Browse Source 
This also caches the TSEG region and therefore increases MTRR usage
a little in some cases.

Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.

Tested on Intel DG41WV, resume from S3 still works fine.

Change-Id: I317c5ca34bd38c3d42bf0d4e929b2a225a8a82dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25597
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2018-04-10 13:34:24 +02:00
parent cf3076eff1
commit 4c65bfc3e8
6 changed files with 76 additions and 29 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/x86/smm/smmrelocate.S
View File

@@ -27,9 +27,6 @@
#include <southbridge/intel/i82801dx/i82801dx.h>
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
#include <southbridge/intel/i82801ix/i82801ix.h>
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)
#include <southbridge/intel/i82801jx/i82801jx.h>
#else
#error "Southbridge needs SMM handler support."
#endif