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soc/amd/picasso: Use read*p

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This avoids compiler warnings on 64bit builds that complains about
casting pointer to non matching integer size.

Change-Id: I29fdb73ae1c0508796a21b650bf4fd1ac6688021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
2022-04-19 21:44:22 +02:00
committed by Felix Held
parent eb8bbb6c04
commit 4c684877d1
3 changed files with 9 additions and 9 deletions
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14
src/soc/amd/common/block/acpi/ivrs.c
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@@ -219,8 +219,8 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_t *ivrs)
ivhd_40->iommu_attributes = ivrs->ivhd.iommu_feature_info & 0xfffe000; ivhd_40->iommu_attributes = ivrs->ivhd.iommu_feature_info & 0xfffe000;
if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) { if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) {
ivhd_40->efr_reg_image_low = read32((void *)ivhd_40->iommu_base_low + 0x30); ivhd_40->efr_reg_image_low = read32p(ivhd_40->iommu_base_low + 0x30);
ivhd_40->efr_reg_image_high = read32((void *)ivhd_40->iommu_base_low + 0x34); ivhd_40->efr_reg_image_high = read32p(ivhd_40->iommu_base_low + 0x34);
} }
current += sizeof(acpi_ivrs_ivhd40_t); current += sizeof(acpi_ivrs_ivhd40_t);
@@ -293,8 +293,8 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs)
ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr; ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr;
if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) { if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) {
ivhd_11->efr_reg_image_low = read32((void *)ivhd_11->iommu_base_low + 0x30); ivhd_11->efr_reg_image_low = read32p(ivhd_11->iommu_base_low + 0x30);
ivhd_11->efr_reg_image_high = read32((void *)ivhd_11->iommu_base_low + 0x34); ivhd_11->efr_reg_image_high = read32p(ivhd_11->iommu_base_low + 0x34);
} }
current += sizeof(acpi_ivrs_ivhd11_t); current += sizeof(acpi_ivrs_ivhd11_t);
@@ -361,9 +361,9 @@ unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
cap_offset_0 = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset); cap_offset_0 = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset);
cap_offset_10 = pci_read_config32(iommu_dev, cap_offset_10 = pci_read_config32(iommu_dev,
ivrs->ivhd.capability_offset + 0x10); ivrs->ivhd.capability_offset + 0x10);
mmio_x18_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x18); mmio_x18_value = read64p(ivrs->ivhd.iommu_base_low + 0x18);
mmio_x30_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x30); mmio_x30_value = read64p(ivrs->ivhd.iommu_base_low + 0x30);
mmio_x4000_value = read64((void *)ivrs->ivhd.iommu_base_low + 0x4000); mmio_x4000_value = read64p(ivrs->ivhd.iommu_base_low + 0x4000);
ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PPR_SUP) ? ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_EXT_FEATURE_PPR_SUP) ?
IVHD_FLAG_PPE_SUP : 0); IVHD_FLAG_PPE_SUP : 0);

2
src/soc/amd/common/block/cpu/smm/smi_apmc_helper.c
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@@ -82,5 +82,5 @@ void handle_smi_store(void)
reg_ebx = io_smi->rbx; reg_ebx = io_smi->rbx;
/* drivers/smmstore/smi.c */ /* drivers/smmstore/smi.c */
io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); io_smi->rax = smmstore_exec(sub_command, (void *)(uintptr_t)reg_ebx);
} }

2
src/soc/amd/picasso/fch.c
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@@ -109,7 +109,7 @@ static void sb_rfmux_config_override(void)
for (port = 0; port < USB_PD_PORT_COUNT; port++) { for (port = 0; port < USB_PD_PORT_COUNT; port++) {
if (cfg->usb_pd_config_override[port].rfmux_override_en) { if (cfg->usb_pd_config_override[port].rfmux_override_en) {
write32((void *)(USB_PD_PORT_CONTROL + PD_PORT_MUX_OFFSET(port)), write32p(USB_PD_PORT_CONTROL + PD_PORT_MUX_OFFSET(port),
cfg->usb_pd_config_override[port].rfmux_config cfg->usb_pd_config_override[port].rfmux_config
| USB_PD_RFMUX_OVERRIDE); | USB_PD_RFMUX_OVERRIDE);
} }