OxPCIe uart: Split PCI bridge control
None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Patrick Georgi
parent
afa7b13b93
commit
4c686f2106
@@ -237,6 +237,35 @@ config PCIEXP_ASPM
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config PCI_BUS_SEGN_BITS
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int
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default 0
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config EARLY_PCI_BRIDGE
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bool "Early PCI bridge"
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depends on PCI
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default n
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help
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While coreboot is executing code from ROM, the coreboot resource
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allocator has not been running yet. Hence PCI devices living behind
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a bridge are not yet visible to the system.
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This option enables static configuration for a single pre-defined
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PCI bridge function on bus 0.
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if EARLY_PCI_BRIDGE
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config EARLY_PCI_BRIDGE_DEVICE
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hex "bridge device"
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default 0x0
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config EARLY_PCI_BRIDGE_FUNCTION
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hex "bridge function"
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default 0x0
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config EARLY_PCI_MMIO_BASE
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hex "MMIO window base"
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default 0x0
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endif # EARLY_PCI_BRIDGE
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endmenu
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menu "VGA BIOS"
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@@ -11,6 +11,7 @@ ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
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ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c
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ramstage-$(CONFIG_ARCH_X86) += pnp_device.c
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ramstage-$(CONFIG_PCI) += pci_ops.c
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ramstage-$(CONFIG_PCI) += pci_early.c
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ramstage-y += smbus_ops.c
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romstage-y += device_romstage.c
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@@ -1,6 +1,8 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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@@ -15,9 +17,14 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#define __SIMPLE_DEVICE__
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#include <arch/io.h>
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <delay.h>
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#ifdef __PRE_RAM__
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unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last)
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{
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@@ -66,3 +73,100 @@ unsigned pci_find_capability(device_t dev, unsigned cap)
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{
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return pci_find_next_capability(dev, cap, 0);
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}
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#endif
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#if CONFIG_EARLY_PCI_BRIDGE
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static void pci_bridge_reset_secondary(device_t p2p_bridge)
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{
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u16 reg16;
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/* First we reset the secondary bus. */
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reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 |= (1 << 6); /* SRESET */
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pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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/* Assume we don't have to wait here forever */
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/* Read back and clear reset bit. */
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reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
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reg16 &= ~(1 << 6); /* SRESET */
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pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
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}
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static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary)
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{
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/* Disable config transaction forwarding. */
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pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
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pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
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/* Enable config transaction forwarding. */
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pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
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pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
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}
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static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size)
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{
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u16 reg16;
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/* Disable MMIO window behind the bridge. */
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reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10);
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if (!size)
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return;
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/* Enable MMIO window behind the bridge. */
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pci_write_config32(p2p_bridge, PCI_MEMORY_BASE,
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((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0));
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reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
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reg16 |= PCI_COMMAND_MEMORY;
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pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
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}
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void pci_early_bridge_init(void)
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{
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int timeout, ret = -1;
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/* No PCI-to-PCI bridges are enabled yet, so the one we try to
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* configure must have its primary on bus 0.
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*/
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pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
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CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
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/* Secondary bus number is mostly irrelevant as we disable
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* configuration transactions right after the probe.
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*/
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u8 secondary = 15;
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u8 dev = 0;
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u32 mmio_base = CONFIG_EARLY_PCI_MMIO_BASE;
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/* Enable configuration and MMIO over bridge. */
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pci_bridge_reset_secondary(p2p_bridge);
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pci_bridge_set_secondary(p2p_bridge, secondary);
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pci_bridge_set_mmio(p2p_bridge, mmio_base, 0x4000);
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for (timeout = 20000; timeout; timeout--) {
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u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID);
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if (id != 0 && id != 0xffffffff && id != 0xffff0001)
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break;
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udelay(10);
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}
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if (timeout != 0)
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ret = pci_early_device_probe(secondary, dev, mmio_base);
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/* Disable MMIO window if we found no suitable device. */
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if (ret)
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pci_bridge_set_mmio(p2p_bridge, 0, 0);
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/* Resource allocator will reconfigure bridges and secondary bus
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* number may change. Thus early device cannot reliably use config
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* transactions from here on, so we may as well disable them.
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*/
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pci_bridge_set_secondary(p2p_bridge, 0);
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}
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#endif /* CONFIG_EARLY_PCI_BRIDGE */
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