Remove extra newlines from the end of all coreboot files.

This removes the newlines from all files found by the new
int-015-final-newlines script.

Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/amd/inagua/buildOpts.c

@@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/amd/olivehill/buildOpts.c

@@ -342,4 +342,3 @@ GPIO_CONTROL   olivehill_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/amd/parmer/buildOpts.c

@@ -343,4 +343,3 @@ GPIO_CONTROL   parmer_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/amd/persimmon/buildOpts.c

@@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/amd/south_station/buildOpts.c

@@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/amd/thatcher/buildOpts.c

@@ -343,4 +343,3 @@ GPIO_CONTROL   thatcher_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/amd/torpedo/buildOpts.c

@@ -219,4 +219,3 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
 #include "PlatformInstall.h"
-

src/mainboard/amd/union_station/buildOpts.c

@@ -294,4 +294,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/asrock/e350m1/buildOpts.c

@@ -293,4 +293,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/asrock/imb-a180/buildOpts.c

@@ -342,4 +342,3 @@ GPIO_CONTROL   imba180_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/asus/f2a85-m/buildOpts.c

@@ -345,4 +345,3 @@ GPIO_CONTROL   f2a85_m_gpio[] = {
 
 /* Moving this include up will break AGESA. */
 #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-

src/mainboard/asus/f2a85-m_le/buildOpts.c

@@ -345,4 +345,3 @@ GPIO_CONTROL   f2a85_m_gpio[] = {
 
 /* Moving this include up will break AGESA. */
 #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-

src/mainboard/bap/ode_e20XX/buildOpts.c

@@ -343,4 +343,3 @@ GPIO_CONTROL   gizmo2_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/biostar/am1ml/buildOpts.c

@@ -342,4 +342,3 @@ GPIO_CONTROL   imba180_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/emulation/qemu-power8/cbmem.c

@@ -22,4 +22,3 @@ void *cbmem_top(void)
 	void *ptr = (void *) ((1ULL << 32) - 1048576);
 	return ptr;
 }
-

src/mainboard/gizmosphere/gizmo/buildOpts.c

@@ -296,4 +296,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/gizmosphere/gizmo2/buildOpts.c

@@ -343,4 +343,3 @@ GPIO_CONTROL   gizmo2_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/google/auron/acpi/video.asl

@@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
 {
 	// TODO (no displays defined yet)
 }
-

src/mainboard/google/auron_paine/acpi/video.asl

@@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
 {
 	// TODO (no displays defined yet)
 }
-

src/mainboard/google/chell/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/cyan/boardid.c

@@ -28,4 +28,3 @@ uint8_t board_id(void)
 #endif
 	return id;
 }
-

src/mainboard/google/cyan/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/cyan/irqroute.h

@@ -42,4 +42,3 @@
 	PIRQ_PIC(F, DISABLE), \
 	PIRQ_PIC(G, DISABLE), \
 	PIRQ_PIC(H, DISABLE)
-

src/mainboard/google/cyan/onboard.h

@@ -81,4 +81,3 @@
 
 #define DPTF_CPU_PASSIVE	88
 #define DPTF_CPU_CRITICAL	90
-

src/mainboard/google/foster/Kconfig.name

@@ -1,3 +1,2 @@
 config BOARD_GOOGLE_FOSTER
 	bool "Foster"
-

src/mainboard/google/foster/bct/sdram-samsung-3GB-204.cfg

@@ -688,4 +688,3 @@ SDRAM[0].McMtsCarveoutRegCtrl                     = 0x00000000;
 #@ tRFC [dvfs dram_timing]                        = 0x000000b4;
 #@ tFC_lpddr4 [dvfs dram_timing hard_coded]       = 0x00000104;
 #@ RL [dvfs dram_timing]                          = 0x00000006;
-

src/mainboard/google/glados/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/guado/acpi/haswell_pci_irqs.asl

@@ -80,4 +80,3 @@ Method(_PRT)
 		})
 	}
 }
-

src/mainboard/google/guado/acpi/superio.asl

@@ -29,4 +29,3 @@
 #define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
 
 #include "superio/ite/it8772f/acpi/superio.asl"
-

src/mainboard/google/guado/acpi/thermal.asl

@@ -337,4 +337,3 @@ Scope (\_TZ)
 		}
 	}
 }
-

src/mainboard/google/guado/acpi/video.asl

@@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
 {
 	// TODO (no displays defined yet)
 }
-

src/mainboard/google/guado/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/guado/mainboard.c

@@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 };
-

src/mainboard/google/jecht/cmos.layout

@@ -130,5 +130,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/jecht/mainboard.c

@@ -146,4 +146,3 @@ static void mainboard_enable(device_t dev)
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 };
-

src/mainboard/google/lars/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/ninja/acpi/video.asl

@@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
 {
 	// TODO (no displays defined yet)
 }
-

src/mainboard/google/ninja/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/oak/Makefile.inc

@@ -30,4 +30,3 @@ ramstage-y += mainboard.c
 ramstage-y += chromeos.c
 ramstage-y += memlayout.ld
 ramstage-y += boardid.c
-

src/mainboard/google/reef/Kconfig.name

@@ -1,3 +1,2 @@
 config BOARD_GOOGLE_REEF
 	bool "Reef"
-

src/mainboard/google/reef/chromeos.fmd

@@ -50,4 +50,3 @@ FLASH 16M {
 	# Device ext --> 0xf7f000 to 0xfff000
 	UNUSED_HOLE@0xfff000 0x1000
 }
-

src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl

@@ -80,4 +80,3 @@ Method(_PRT)
 		})
 	}
 }
-

src/mainboard/google/rikku/acpi/superio.asl

@@ -29,4 +29,3 @@
 #define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
 
 #include "superio/ite/it8772f/acpi/superio.asl"
-

src/mainboard/google/rikku/acpi/thermal.asl

@@ -337,4 +337,3 @@ Scope (\_TZ)
 		}
 	}
 }
-

src/mainboard/google/rikku/acpi/video.asl

@@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
 {
 	// TODO (no displays defined yet)
 }
-

src/mainboard/google/rikku/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/rikku/mainboard.c

@@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 };
-

src/mainboard/google/tidus/acpi/haswell_pci_irqs.asl

@@ -80,4 +80,3 @@ Method(_PRT)
 		})
 	}
 }
-

src/mainboard/google/tidus/acpi/superio.asl

@@ -29,4 +29,3 @@
 #define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
 
 #include "superio/ite/it8772f/acpi/superio.asl"
-

src/mainboard/google/tidus/acpi/thermal.asl

@@ -445,4 +445,3 @@ Scope (\_TZ)
 		}
 	}
 }
-

src/mainboard/google/tidus/acpi/video.asl

@@ -36,4 +36,3 @@ Method(BRTN,1,Serialized)
 {
 	// TODO (no displays defined yet)
 }
-

src/mainboard/google/tidus/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/google/tidus/mainboard.c

@@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 };
-

src/mainboard/hp/abm/buildOpts.c

@@ -356,4 +356,3 @@ GPIO_CONTROL   hp_abm_gpio[] = {
 #define DFLT_VRM_SLEW_RATE              (5000)
 
 #include "PlatformInstall.h"
-

src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c

@@ -389,4 +389,3 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
 
 /* AGESA nonsense: this header depends on the definitions above */
 #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-

src/mainboard/intel/amenia/Kconfig.name

@@ -1,3 +1,2 @@
 config BOARD_INTEL_AMENIA
 	bool "Amenia"
-

src/mainboard/intel/amenia/chromeos.fmd

@@ -34,4 +34,3 @@ FLASH 8M {
     }
     DEVICE_EXTENSION@7M 1M
 }
-

src/mainboard/intel/apollolake_rvp/Makefile.inc

@@ -1,2 +1 @@
 #Nothing here yet
-

src/mainboard/intel/kunimitsu/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/intel/strago/boardid.c

@@ -28,4 +28,3 @@ uint8_t board_id(void)
 #endif
 	return id;
 }
-

src/mainboard/intel/strago/cmos.layout

@@ -131,5 +131,3 @@ enumerations
 checksums
 
 checksum 392 415 984
-
-

src/mainboard/intel/strago/irqroute.h

@@ -42,4 +42,3 @@
 	PIRQ_PIC(F, DISABLE), \
 	PIRQ_PIC(G, DISABLE), \
 	PIRQ_PIC(H, DISABLE)
-

src/mainboard/jetway/nf81-t56n-lf/buildOpts.c

@@ -299,4 +299,3 @@ const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 /* AGESA nonsense: this header depends on the definitions above */
 /* Instantiate all solution relevant data. */
 #include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>
-

src/mainboard/lenovo/g505s/buildOpts.c

@@ -389,4 +389,3 @@ SCI_MAP_CONTROL lenovo_g505s_sci_map[] = {
 
 /* AGESA nonsense: this header depends on the definitions above */
 #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
-

src/mainboard/lenovo/t400/acpi/ich9_pci_irqs.asl

@@ -102,4 +102,3 @@ If (PICM) {
 		// Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
 	})
 }
-

src/mainboard/lenovo/t400/acpi/platform.asl

@@ -82,4 +82,3 @@ Scope(\_SB)
 		// TRAP(43) // TODO
 	}
 }
-

src/mainboard/lenovo/t400/cmos.layout

@@ -146,4 +146,3 @@ enumerations
 checksums
 
 checksum 392 983 984
-

src/mainboard/lenovo/t400/mainboard.c

@@ -42,4 +42,3 @@ static void mainboard_enable(device_t dev)
 struct chip_operations mainboard_ops = {
 	.enable_dev = mainboard_enable,
 };
-

src/mainboard/lenovo/t400/romstage.c

@@ -190,4 +190,3 @@ void mainboard_romstage_entry(unsigned long bist)
 #endif
 	printk(BIOS_SPEW, "exit main()\n");
 }
-

src/mainboard/lippert/frontrunner-af/buildOpts.c

@@ -295,4 +295,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/lippert/toucan-af/buildOpts.c

@@ -295,4 +295,3 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 
 // Instantiate all solution relevant data.
 #include "PlatformInstall.h"
-

src/mainboard/supermicro/h8qgi/buildOpts.c

@@ -435,4 +435,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 */
 
 #include "MaranelloInstall.h"
-

src/mainboard/supermicro/h8scm/buildOpts.c

@@ -339,4 +339,3 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] =
  */
 
 #include "SanMarinoInstall.h"
-

src/mainboard/tyan/s8226/buildOpts.c

@@ -435,4 +435,3 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
 */
 
 #include "SanMarinoInstall.h"
-