mb/google/brox/jubilant: Disable devcies and GPIOs by fw_config

1.Set unused device's GPIOs to NC based on fw_config.
2.Disable config for nvme, ufs and CNVi based on fw_config.
3.Add fw_config STORAGE_UNKNOWN to enable all storages
  for the first boot in factory.

  BUG=None
  TEST=emerge-brox coreboot chromeos-bootiamge
       check fw_config messages in ap log
       verify devices on/off by fw_config on jubilant

Change-Id: I8d9f4edea454e0861f91261bf13fa80572d0a181
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>

src/mainboard/google/brox/variants/jubilant/Makefile.mk

@@ -5,6 +5,7 @@ bootblock-y += gpio.c
 romstage-y += gpio.c
 romstage-y += memory.c
 
+ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-$(CONFIG_FW_CONFIG) += variant.c
 ramstage-y += gpio.c
 ramstage-y += ramstage.c

src/mainboard/google/brox/variants/jubilant/fw_config.c

@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <fw_config.h>
+
+static const struct pad_config fp_disable_pads[] = {
+	/* D2  : ISH_GP2 ==> EN_FP_PWR (NC) */
+	PAD_NC(GPP_D2, NONE),
+	/* GPP_D3 : IPCH_FP_BOOT0 (active high) (NC) */
+	PAD_NC(GPP_D3, NONE),
+	/* GPP_D15 : FPMCU_RST_J_SUB_L (active low) (NC) */
+	PAD_NC(GPP_D15, NONE),
+	/* GPP_F15 : FP GSPI INT (NC)  */
+	PAD_NC(GPP_F15, NONE),
+	/* GPP_F11 : FP GSPI CLK (NC) */
+	PAD_NC(GPP_F11, NONE),
+	/* GPP_F12 : FP GSPI DO (NC) */
+	PAD_NC(GPP_F12, NONE),
+	/* GPP_F13 : FP GSPI DI (NC) */
+	PAD_NC(GPP_F13, NONE),
+	/* GPP_F16 : FP GSPI CS (NC) */
+	PAD_NC(GPP_F16, NONE),
+};
+
+static const struct pad_config lte_disable_pads[] = {
+	/* GPP_E11 : WWAN_CFG0 */
+	PAD_NC(GPP_E11, NONE),
+	/* GPP_E17 : WWAN_CFG02 */
+	PAD_NC(GPP_E17, NONE),
+	/* GPP_D7 :WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_D7, NONE),
+	/* GPP_D5 : WWAN_SAR_ODL */
+	PAD_NC(GPP_D5, NONE),
+	/* GPP_F21 : WWAN_FCPO_L */
+	PAD_NC(GPP_F21, NONE),
+	/* GPP_S4 : WWAN_WLAN_COEX1 */
+	PAD_NC(GPP_S4, NONE),
+	/* GPP_S5 : WWAN_WLAN_COEX2 */
+	PAD_NC(GPP_S5, NONE),
+	/* GPP_F6 : WWAN_WLAN_COEX3 */
+	PAD_NC(GPP_F6, NONE),
+	/* GPP_A12 : WWAN_PWR_EN */
+	PAD_NC(GPP_A12, NONE),
+	/* GPP_H23 : WWAN_RST_L */
+	PAD_NC(GPP_H23, NONE),
+};
+
+static const struct pad_config nvme_disable_pads[] = {
+	/* GPP_F9 : SSD_PERST_L */
+	PAD_NC(GPP_F9, NONE),
+	/* GPP_D11 : EN_PP3300_SSD (NC) */
+	PAD_NC(GPP_D11, NONE),
+	/* GPP_D8 : SSD_CLKREQ_ODL */
+	PAD_NC(GPP_D8, NONE),
+};
+
+static void fw_config_handle(void *unused)
+{
+	if (!fw_config_is_provisioned()) {
+		printk(BIOS_WARNING, "FW_CONFIG is not provisioned. Exiting...\n");
+		return;
+	}
+
+	if (fw_config_probe(FW_CONFIG(FPMCU, FPMCU_ABSENT))) {
+		printk(BIOS_INFO, "Disable Fingerprint GPIOs by fw_config.\n");
+		gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads));
+	}
+
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) {
+		printk(BIOS_INFO, "Disable LTE-related GPIO pins by fw_config.\n");
+		gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
+	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNPROVISIONED))) {
+		if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
+			printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n");
+			gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads));
+		}
+	}
+}
+BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

src/mainboard/google/brox/variants/jubilant/overridetree.cb

@@ -1,8 +1,8 @@
 fw_config
 	field STORAGE 2 3
-		option STORAGE_UNKNOWN			0
 		option STORAGE_UFS			1
 		option STORAGE_NVME			2
+		option STORAGE_UNPROVISIONED		3
 	end
 	field WIFI_BT 4 4
 		option WIFI_BT_CNVI			0
@@ -294,6 +294,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			probe STORAGE STORAGE_NVME
+			probe STORAGE STORAGE_UNPROVISIONED
 		end
 		device ref pcie_rp5 on
 			register "pch_pcie_rp[PCH_RP(5)]" = "{
@@ -331,9 +332,11 @@ chip soc/intel/alderlake
 				device generic 0 alias ish_conf on end
 			end
 			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNPROVISIONED
 		end
 		device ref ufs on
 			probe STORAGE STORAGE_UFS
+			probe STORAGE STORAGE_UNPROVISIONED
 		end
 		device ref i2c0 on
 			chip drivers/i2c/generic

src/mainboard/google/brox/variants/jubilant/variant.c

@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <baseboard/variants.h>
 #include <chip.h>
+#include <device/device.h>
 #include <fw_config.h>
 #include <sar.h>
 
@@ -11,6 +12,11 @@ void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 	if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI))) {
 		printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
 		config->cnvi_bt_core = true;
+		config->cnvi_bt_audio_offload = true;
+	} else {
+		printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n");
+		config->cnvi_bt_core = false;
+		config->cnvi_bt_audio_offload = false;
 	}
 }
 
@@ -18,3 +24,26 @@ const char *get_wifi_sar_cbfs_filename(void)
 {
 	return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT));
 }
+
+void variant_devtree_update(void)
+{
+	struct device *ufs = DEV_PTR(ufs);
+	struct device *ish = DEV_PTR(ish);
+	struct device *nvme_rp = DEV_PTR(pcie4_0);
+
+	if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNPROVISIONED))) {
+		printk(BIOS_INFO, "fw_config storage is unknown so enable all storage devices.\n");
+		return;
+	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
+		printk(BIOS_INFO, "NVMe disabled by fw_config.\n");
+		nvme_rp->enabled = 0;
+	}
+
+	if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+		printk(BIOS_INFO, "UFS disabled by fw_config.\n");
+		ufs->enabled = 0;
+		ish->enabled = 0;
+	}
+}