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soc/mediatek/mt8192: initialize DRAM using vendor reference code

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Mediatek has released the reference implementation for DRAM
initialization in vendorcode/mediatek/mt8192/dramc (CB:50294)
so we want to use it to replace the derived calibration code
in soc folder.

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2b2f41d774c6b85f106867144fb0b29a4a1bdfcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
Huayang Duan 2020-06-24 10:14:32 +08:00 committed by Hung-Te Lin
parent e8c681cc62
commit 4c7bf7eaaf
14 changed files with 5 additions and 12631 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/soc/mediatek/mt8192/Kconfig
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@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8192
select ARCH_ROMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64
select ARCH_RAMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64
select ARM64_USE_ARM_TRUSTED_FIRMWARE select ARM64_USE_ARM_TRUSTED_FIRMWARE
select HAVE_DEBUG_RAM_SETUP
select HAVE_UART_SPECIAL select HAVE_UART_SPECIAL
select SOC_MEDIATEK_COMMON select SOC_MEDIATEK_COMMON
@ -17,35 +18,6 @@ config VBOOT
select VBOOT_SEPARATE_VERSTAGE select VBOOT_SEPARATE_VERSTAGE
select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE
config DEBUG_DRAM
bool "Output verbose DRAM related debug messages"
default y
help
This option enables additional DRAM related debug messages.
config MT8192_DRAM_EMCP
bool
default y
help
The eMCP platform should select this option to run at different DRAM
frequencies.
config MT8192_DRAM_DVFS
bool
default n
help
This option enables DRAM calibration with multiple frequencies (low,
medium and high frequency groups, with total 7 frequencies) for DVFS
feature. All supported data rates are: 800, 1200, 1600, 1866, 2400,
3200, 4266.
config MEMORY_TEST
bool
default y
help
This option enables memory basic compare test to verify the DRAM read
or write is as expected.
config DPM_DM_FIRMWARE config DPM_DM_FIRMWARE
string string
default "dpm.dm" default "dpm.dm"

8
src/soc/mediatek/mt8192/Makefile.inc
View File

@ -29,14 +29,12 @@ verstage-y += ../common/uart.c
romstage-y += ../common/auxadc.c romstage-y += ../common/auxadc.c
romstage-y += ../common/cbmem.c romstage-y += ../common/cbmem.c
romstage-y += ../common/dram_init.c romstage-y += ../common/dram_init.c
romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c romstage-y += ../common/dramc_param.c
romstage-y += dramc_utility.c dramc_dvfs.c
romstage-y += emi.c
romstage-y += ../common/flash_controller.c romstage-y += ../common/flash_controller.c
romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/gpio.c gpio.c
romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/i2c.c i2c.c
romstage-y += ../common/memory.c ../common/memory_test.c
romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/mmu_operations.c mmu_operations.c
romstage-y += ../common/memory.c ../common/dramc_param.c ../common/memory_test.c
romstage-y += ../common/pll.c pll.c romstage-y += ../common/pll.c pll.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
romstage-y += ../common/timer.c romstage-y += ../common/timer.c
@ -53,7 +51,6 @@ ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
ramstage-y += ../common/flash_controller.c ramstage-y += ../common/flash_controller.c
ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/gpio.c gpio.c
ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/i2c.c i2c.c
ramstage-y += emi.c
ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
ramstage-y += ../common/mcu.c ramstage-y += ../common/mcu.c
ramstage-y += mcupm.c ramstage-y += mcupm.c
@ -97,6 +94,7 @@ BL31_MAKEARGS += PLAT=mt8192
CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include
CPPFLAGS_common += -Isrc/vendorcode/mediatek/mt8192/include
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@

190
src/soc/mediatek/mt8192/dramc_dvfs.c
View File

@ -1,190 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/dramc_pi_api.h>
#include <soc/dramc_register.h>
void enable_dfs_hw_mode_clk(void)
{
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3,
MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 0x3,
MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 0x1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl,
MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0x1,
MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0x1,
MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL_MODE, 0x0,
MISC_CLK_CTRL_DVFS_MEM_CK_MUX_SEL, 0x1);
}
}
void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level)
{
u8 shu_ack = 0;
u8 tmp_level;
u8 pll_mode = *(cali->pll_mode);
u32 *shu_ack_reg = &mtk_dpm->status_4;
if (pll_mode == PHYPLL_MODE) {
dramc_dbg("Disable CLRPLL\n");
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0);
} else {
dramc_dbg("Disable PHYPLL\n");
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0);
}
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
shu_ack |= (0x1 << chn);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 1);
if (shu_level == DRAM_DFS_SHU0)
tmp_level = shu_level;
else
tmp_level = 1;
if (pll_mode == PHYPLL_MODE) {
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 1);
}
dramc_dbg("Enable CLRPLL\n");
} else {
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_PHYPLL2_SHU_EN, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_DR_SHU_LEVEL, tmp_level);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_PHYPLL_SHU_EN, 1);
}
dramc_dbg("Enable PHYPLL\n");
}
udelay(1);
if (pll_mode == PHYPLL_MODE)
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 1);
else
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 1);
udelay(20);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 1);
while ((READ32_BITFIELD(shu_ack_reg, LPIF_STATUS_4_SHU_EN_ACK) & shu_ack) != shu_ack)
dramc_dbg("Waiting shu_en ack\n");
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_DR_SHU_EN, 0);
if (pll_mode == PHYPLL_MODE)
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.phypll0, PHYPLL0_RG_RPHYPLL_EN, 0);
else
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.clrpll0, CLRPLL0_RG_RCLRPLL_EN, 0);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl,
MISC_RG_DFS_CTRL_RG_DDRPHY_FB_CK_EN, 0);
dramc_dbg("Shuffle flow completed\n");
pll_mode = !pll_mode;
*(cali->pll_mode) = pll_mode;
}
void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst)
{
u8 tmp;
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_SLV_SEL, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SRAM_WR_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_WR_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, src);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, dst);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 1);
do {
tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_SRAM_DONE);
tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_APB_DONE) << 1);
dramc_dbg("Waiting dramc to shuffle sram, tmp: %u\n", tmp);
} while (tmp != 0x3);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 0);
}
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SRAM_WR_MODE, 0);
}
void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst)
{
u8 tmp;
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_SLV_SEL, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SRAM_WR_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_APB_WR_MODE, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_APB, dst);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_SHU_LEVEL_SRAM, src);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 1);
do {
tmp = READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_SRAM_DONE);
tmp |= (READ32_BITFIELD(&ch[chn].phy_nao.misc_dma_debug0,
MISC_DMA_DEBUG0_APB_DONE) << 1);
dramc_dbg("Waiting shuffle sram to dramc, tmp: %u\n", tmp);
} while (tmp != 0x3);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_DMA_FIRE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_STEP_EN_MODE, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0,
MISC_SRAM_DMA0_SW_MODE, 0);
}
}

4710
src/soc/mediatek/mt8192/dramc_pi_basic_api.c
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File diff suppressed because it is too large Load Diff

656
src/soc/mediatek/mt8192/dramc_pi_calibration_api.c
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@ -1,656 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/dramc_pi_api.h>
#include <soc/dramc_register.h>
static const u8 imp_vref_sel[ODT_MAX][IMP_DRV_MAX] = {
/* DRVP DRVN ODTP ODTN */
[ODT_OFF] = {0x37, 0x33, 0x00, 0x37},
[ODT_ON] = {0x3a, 0x33, 0x00, 0x3a},
};
static void dramc_imp_cal_vref_sel(dram_odt_state odt, imp_drv_type drv_type)
{
u8 vref_tmp = imp_vref_sel[odt][drv_type];
switch (drv_type) {
case DRVP:
SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12,
SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVP, vref_tmp);
break;
case DRVN:
SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12,
SHU_CA_CMD12_RG_RIMP_VREF_SEL_DRVN, vref_tmp);
break;
case ODTN:
SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12,
SHU_CA_CMD12_RG_RIMP_VREF_SEL_ODTN, vref_tmp);
break;
default:
die("Can't support drv_type %d\n", drv_type);
break;
}
}
static u32 dramc_sw_imp_cal_result(imp_drv_type drv_type)
{
u32 drive = 0, cal_res = 0;
u32 change = (drv_type == DRVP) ? 1 : 0;
static const char *const drv_type_str[IMP_DRV_MAX] = {
[DRVP] = "DRVP",
[DRVN] = "DRVN",
[ODTP] = "ODTP",
[ODTN] = "ODTN",
};
if (drv_type >= IMP_DRV_MAX)
die("Can't support drv_type %d", drv_type);
const char *drv_str = drv_type_str[drv_type];
for (drive = 0; drive < 32; drive++) {
if (drv_type == DRVP)
SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1,
SHU_MISC_IMPCAL1_IMPDRVP, drive);
else if (drv_type == DRVN || drv_type == ODTN)
SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1,
SHU_MISC_IMPCAL1_IMPDRVN, drive);
udelay(1);
cal_res = READ32_BITFIELD(&ch[0].phy_nao.misc_phy_rgs_cmd,
MISC_PHY_RGS_CMD_RGS_RIMPCALOUT);
dramc_dbg("OCD %s=%d ,CALOUT=%d\n", drv_str, drive, cal_res);
if (cal_res == change) {
dramc_info("%s calibration passed! result=%d\n", drv_str, drive);
break;
}
}
if (drive == 32) {
drive = 31;
dramc_err("OCD %s calibration failed! %s=%d\n", drv_str, drv_str, drive);
}
return drive;
}
void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp)
{
const u8 chn = 0;
u8 i_chn, enp, enn;
u32 bc_bak, impcal_bak, cal_res;
u32 drvp_result = 0xff, odtn_result = 0xff, drvn_result = 0xff;
bc_bak = dramc_get_broadcast();
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
for (i_chn = 0; i_chn < CHANNEL_MAX; i_chn++) {
SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_lp_ctrl,
MISC_LP_CTRL_RG_ARDMSUS_10, 0x0,
MISC_LP_CTRL_RG_ARDMSUS_10_LP_SEL, 0x0,
MISC_LP_CTRL_RG_RIMP_DMSUS_10, 0x0,
MISC_LP_CTRL_RG_RIMP_DMSUS_10_LP_SEL, 0x0);
SET32_BITFIELDS(&ch[i_chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_HW, 0);
}
impcal_bak = read32(&ch[chn].phy_ao.misc_impcal);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1, MISC_IMP_CTRL1_RG_RIMP_PRE_EN, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal,
MISC_IMPCAL_IMPCAL_CALI_ENN, 0,
MISC_IMPCAL_IMPCAL_IMPPDP, 1,
MISC_IMPCAL_IMPCAL_IMPPDN, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_imp_ctrl1,
MISC_IMP_CTRL1_RG_IMP_EN, 1,
MISC_IMP_CTRL1_RG_RIMP_DDR3_SEL, 0,
MISC_IMP_CTRL1_RG_RIMP_VREF_EN, 1,
MISC_IMP_CTRL1_RG_RIMP_DDR4_SEL, 1);
udelay(1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal, MISC_IMPCAL_IMPCAL_CALI_EN, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1,
SHU_MISC_IMPCAL1_IMPDRVN, 0,
SHU_MISC_IMPCAL1_IMPDRVP, 0);
for (imp_drv_type drv_type = DRVP; drv_type < IMP_DRV_MAX; drv_type++) {
if (drv_type == ODTP)
continue;
dramc_imp_cal_vref_sel(odt, drv_type);
switch (drv_type) {
case DRVP:
enp = 0x1;
enn = 0x0;
drvp_result = 0;
break;
case DRVN:
case ODTN:
enp = 0x0;
enn = (drv_type == DRVN) ? 0x0 : 0x1;
break;
default:
die("Can't support drv_type %d\n", drv_type);
break;
}
SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal,
MISC_IMPCAL_IMPCAL_CALI_ENP, enp);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_impcal,
MISC_IMPCAL_IMPCAL_CALI_ENN, enn);
SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1,
SHU_MISC_IMPCAL1_IMPDRVP, drvp_result);
SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12,
SHU_CA_CMD12_RG_RIMP_DRV05, 0);
cal_res = dramc_sw_imp_cal_result(drv_type);
switch (drv_type) {
case DRVP:
drvp_result = cal_res;
break;
case DRVN:
drvn_result = cal_res;
break;
case ODTN:
odtn_result = cal_res;
break;
default:
die("Can't support drv_type %d\n", drv_type);
break;
}
}
imp->result[odt][DRVP] = drvp_result;
imp->result[odt][DRVN] = drvn_result;
imp->result[odt][ODTP] = 0;
imp->result[odt][ODTN] = odtn_result;
dramc_info("freq_region=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n",
odt, drvp_result, drvn_result, odtn_result);
write32(&ch[chn].phy_ao.misc_impcal, impcal_bak);
dramc_set_broadcast(bc_bak);
}
void dramc_sw_impedance_save_register(const struct ddr_cali *cali)
{
u8 ca_term, dq_term;
u32 bc_bak = dramc_get_broadcast();
const u32 (*result)[IMP_DRV_MAX] = cali->impedance.result;
struct ddrphy_ao_regs *phy_ao = &ch[0].phy_ao;
ca_term = get_odt_state(cali);
dq_term = (get_freq_group(cali) < DDRFREQ_2133) ? ODT_OFF : ODT_ON;
dramc_set_broadcast(DRAMC_BROADCAST_ON);
SET32_BITFIELDS(&phy_ao->shu_misc_drving1,
SHU_MISC_DRVING1_DQDRVP2, result[dq_term][DRVP],
SHU_MISC_DRVING1_DQDRVN2, result[dq_term][DRVN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving2,
SHU_MISC_DRVING2_DQDRVP1, result[dq_term][DRVP],
SHU_MISC_DRVING2_DQDRVN1, result[dq_term][DRVN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving3,
SHU_MISC_DRVING3_DQODTP2, result[dq_term][ODTP],
SHU_MISC_DRVING3_DQODTN2, result[dq_term][ODTN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving4,
SHU_MISC_DRVING4_DQODTP1, result[dq_term][ODTP],
SHU_MISC_DRVING4_DQODTN1, result[dq_term][ODTN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving1,
SHU_MISC_DRVING1_DQSDRVP2, result[dq_term][DRVP],
SHU_MISC_DRVING1_DQSDRVN2, result[dq_term][DRVN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving1,
SHU_MISC_DRVING1_DQSDRVP1, result[dq_term][DRVP],
SHU_MISC_DRVING1_DQSDRVN1, result[dq_term][DRVN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving3,
SHU_MISC_DRVING3_DQSODTP2, result[dq_term][ODTP],
SHU_MISC_DRVING3_DQSODTN2, result[dq_term][ODTN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving3,
SHU_MISC_DRVING3_DQSODTP, result[dq_term][ODTP],
SHU_MISC_DRVING3_DQSODTN, result[dq_term][ODTN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving2,
SHU_MISC_DRVING2_CMDDRVP2, result[ca_term][DRVP],
SHU_MISC_DRVING2_CMDDRVN2, result[ca_term][DRVN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving2,
SHU_MISC_DRVING2_CMDDRVP1, result[ca_term][DRVP],
SHU_MISC_DRVING2_CMDDRVN1, result[ca_term][DRVN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving4,
SHU_MISC_DRVING4_CMDODTP2, result[ca_term][ODTP],
SHU_MISC_DRVING4_CMDODTN2, result[ca_term][ODTN]);
SET32_BITFIELDS(&phy_ao->shu_misc_drving4,
SHU_MISC_DRVING4_CMDODTP1, result[ca_term][ODTP],
SHU_MISC_DRVING4_CMDODTN1, result[ca_term][ODTN]);
SET32_BITFIELDS(&phy_ao->misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVP, 0xF);
SET32_BITFIELDS(&phy_ao->misc_shu_drving8, MISC_SHU_DRVING8_CS_DRVN, 0x14);
dramc_set_broadcast(bc_bak);
}
static void dramc_phy_reset(u8 chn)
{
SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9,
B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0,
B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0);
SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9,
B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0,
B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0);
udelay(1);
SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq9,
B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 1,
B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq9,
B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 1,
B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 1);
SET32_BITFIELDS(&ch[chn].phy_ao.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0);
SET32_BITFIELDS(&ch[chn].ao.rx_set0, RX_SET0_RDATRST, 0);
}
static int dramc_8_phase_cal_find_best_dly(u8 phase_sm, u8 ph_dly, u8 ph_dly_back,
int *ph_dly_final, int *ph_dly_loop_break)
{
const u8 early_break_cnt = 5;
static u8 loop_cnt = 0;
static u16 r0 = 0xffff, r180 = 0xffff, r_tmp = 0xffff, p_tmp = 0xffff;
s16 err_code;
static s16 err_code_min = 0x7fff;
u16 dqs_dly;
const u16 jm_dly_start = 0, jm_dly_end = 512, jm_dly_step = 1;
u32 sample_cnt, ones_cnt;
u8 dqs_level = DQS_LEVEL_UNKNOWN;
dramc_dbg("8PH dly = %u\n", ph_dly);
*ph_dly_loop_break = 0;
SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq1,
SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly);
SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq1,
SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly);
SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd1,
SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly);
for (dqs_dly = jm_dly_start; dqs_dly < jm_dly_end; dqs_dly += jm_dly_step) {
/* Set DQS delay */
SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2,
B0_PHY2_RG_RX_ARDQS_JM_DLY_B0, dqs_dly);
SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2,
B1_PHY2_RG_RX_ARDQS_JM_DLY_B1, dqs_dly);
dramc_phy_reset(0);
SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
MISC_DUTYSCAN1_REG_SW_RST, 1);
SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
MISC_DUTYSCAN1_REG_SW_RST, 0);
SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1);
udelay(10);
SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1,
MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0);
sample_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_toggle_cnt,
MISC_DUTY_TOGGLE_CNT_TOGGLE_CNT);
ones_cnt = READ32_BITFIELD(&ch[0].phy_nao.misc_duty_dqs0_err_cnt,
MISC_DUTY_DQS0_ERR_CNT_DQS0_ERR_CNT);
if (ones_cnt < sample_cnt / 2) {
if (dqs_level == DQS_LEVEL_UNKNOWN)
dramc_dbg("[L] %u, %8u\n", dqs_dly, ones_cnt);
dqs_level = 0;
} else if (dqs_level == 0) {
dqs_level = 1;
dramc_dbg("[H] %u, %8u\n", dqs_dly, ones_cnt);
if (phase_sm == DQS_8PH_DEGREE_0) {
r0 = dqs_dly;
dramc_dbg("R0 = %u\n", r0);
} else if (phase_sm == DQS_8PH_DEGREE_180) {
r180 = dqs_dly;
if (r180 <= r0) {
dqs_level = DQS_LEVEL_UNKNOWN;
continue;
}
r_tmp = r0 + ((r180 - r0) >> 2);
dramc_dbg("R = %u, R180 = %u\n", r_tmp, r180);
} else if (phase_sm == DQS_8PH_DEGREE_45) {
p_tmp = dqs_dly;
dramc_dbg("p_tmp = %u, R0 = %u\n", p_tmp, r0);
if (p_tmp <= r0) {
dqs_level = DQS_LEVEL_UNKNOWN;
continue;
}
err_code = ABS(p_tmp - r_tmp);
if (err_code == 0) {
*ph_dly_final = ph_dly;
*ph_dly_loop_break = 1;
} else if (err_code < err_code_min) {
err_code_min = err_code;
*ph_dly_final = ph_dly;
loop_cnt = 0;
} else {
loop_cnt++;
if (loop_cnt > early_break_cnt)
*ph_dly_loop_break = 1;
}
dramc_dbg("diff (P-R) = %d, min = %d, break count = %u\n",
err_code, err_code_min, loop_cnt);
} else {
die("Invalid phase_sm: %u!\n", phase_sm);
}
break;
}
}
if (dqs_level == DQS_LEVEL_UNKNOWN || dqs_level == 0) {
*ph_dly_final = ph_dly_back;
dramc_err("8-Phase SM_%u failed, falling back to default\n", phase_sm);
return 0;
} else if (*ph_dly_loop_break) {
return -1;
}
return -2;
}
static void dramc_8_phase_cal_set_best_dly(const struct ddr_cali *cali, u8 ph_dly_back)
{
u8 dqsien_pi;
u8 phase_sm, ph_dly, ph_start, ph_end;
int ph_dly_loop_break;
int ph_dly_final = 0xff; /* default delay: 0xff */
for (phase_sm = DQS_8PH_DEGREE_0; phase_sm < DQS_8PH_DEGREE_MAX; phase_sm++) {
switch (phase_sm) {
case DQS_8PH_DEGREE_0:
dqsien_pi = 16;
ph_start = 0;
ph_end = 1;
break;
case DQS_8PH_DEGREE_180:
dqsien_pi = 48;
ph_start = 0;
ph_end = 1;
break;
case DQS_8PH_DEGREE_45:
dqsien_pi = 24;
ph_start = 0;
ph_end = 32;
break;
default:
die("Invalid phase_sm: %u!\n", phase_sm);
return;
}
dramc_dbg("8-Phase SM_%u, 8PH_dly (%u~%u), DQSIEN PI = %u, 8PH_Dly = %u\n",
phase_sm, ph_start, ph_end, dqsien_pi, ph_dly_back);
for (u8 rk = RANK_0; rk < cali->support_ranks; rk++)
SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[rk].shu_rk_b0_dqsien_pi_dly,
SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, dqsien_pi);
for (ph_dly = ph_start; ph_dly < ph_end; ph_dly++) {
int ret = dramc_8_phase_cal_find_best_dly(phase_sm, ph_dly,
ph_dly_back, &ph_dly_final, &ph_dly_loop_break);
if (ret == 0)
goto final_found;
if (ph_dly_loop_break)
break;
}
}
final_found:
dramc_dbg("8 phase calibration ph_dly_final = %u\n", ph_dly_final);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq1,
SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0, ph_dly_final);
SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq1,
SHU_B1_DQ1_RG_ARPI_MIDPI_8PH_DLY_B1, ph_dly_final);
SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd1,
SHU_CA_CMD1_RG_ARPI_MIDPI_8PH_DLY_CA, ph_dly_final);
}
}
void dramc_8_phase_cal(const struct ddr_cali *cali)
{
u8 ph_dly_back = 0;
dram_freq_grp freq_group = cali->freq_group;
/* ch0 and ch1 of phy_ao */
struct ddrphy_ao_regs *phy_ao = &ch[0].phy_ao;
struct ddrphy_ao_regs *phy_ao_ch1 = &ch[1].phy_ao;
if (freq_group < DDRFREQ_2133) {
dramc_info("Freq %u < 2133, do not need do 8-Phase\n", get_frequency(cali));
return;
}
struct reg_bak regs_bak[] = {
{&phy_ao->misc_dutyscan1},
{&phy_ao->dvs_b[0].b0_dq6},
{&phy_ao->dvs_b[1].b0_dq6},
{&phy_ao->dvs_b[0].b0_dq5},
{&phy_ao->dvs_b[1].b0_dq5},
{&phy_ao->dvs_b[0].b0_dq3},
{&phy_ao->dvs_b[1].b0_dq3},
{&phy_ao->misc_ctrl1},
{&phy_ao->misc_ctrl4},
{&phy_ao->dvs_b[0].b0_phy2},
{&phy_ao->dvs_b[1].b0_phy2},
{&phy_ao->byte[0].shu_b0_dll_arpi2},
{&phy_ao->byte[1].shu_b0_dll_arpi2},
{&phy_ao->byte[0].shu_b0_dq11},
{&phy_ao->byte[1].shu_b0_dq11},
{&phy_ao->shu_ca_cmd11},
{&phy_ao->misc_stbcal},
{&phy_ao->byte[0].rk[0].shu_rk_b0_dqsien_pi_dly},
{&phy_ao->byte[0].rk[1].shu_rk_b0_dqsien_pi_dly},
{&phy_ao->misc_jmeter},
{&phy_ao->misc_shu_stbcal},
{&phy_ao->shu_ca_dll1},
{&phy_ao->byte[0].shu_b0_dll1},
{&phy_ao->byte[1].shu_b0_dll1},
{&phy_ao->dvs_b[0].b0_dq2},
{&phy_ao->dvs_b[1].b0_dq2},
{&phy_ao->ca_cmd2},
{&phy_ao->byte[0].shu_b0_dq13},
{&phy_ao->byte[1].shu_b0_dq13},
{&phy_ao->shu_ca_cmd13},
{&phy_ao_ch1->shu_ca_dll1},
{&phy_ao_ch1->byte[0].shu_b0_dll1},
{&phy_ao_ch1->byte[1].shu_b0_dll1},
{&phy_ao_ch1->dvs_b[0].b0_dq2},
{&phy_ao_ch1->dvs_b[1].b0_dq2},
{&phy_ao_ch1->ca_cmd2},
{&phy_ao_ch1->byte[0].shu_b0_dq13},
{&phy_ao_ch1->byte[1].shu_b0_dq13},
{&phy_ao_ch1->shu_ca_cmd13},
};
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
regs_bak[i].value = read32(regs_bak[i].addr);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
phy_ao = &ch[chn].phy_ao;
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq2,
B0_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B0, 0,
B0_DQ2_RG_TX_ARDQS_OE_TIE_EN_B0, 1,
B0_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B0, 0,
B0_DQ2_RG_TX_ARWCK_OE_TIE_EN_B0, 1,
B0_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B0, 0,
B0_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B0, 1,
B0_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B0, 0,
B0_DQ2_RG_TX_ARDQM_OE_TIE_EN_B0, 1,
B0_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B0, 0,
B0_DQ2_RG_TX_ARDQ_OE_TIE_EN_B0, 0xff);
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq2,
B1_DQ2_RG_TX_ARDQS_OE_TIE_SEL_B1, 0,
B1_DQ2_RG_TX_ARDQS_OE_TIE_EN_B1, 1,
B1_DQ2_RG_TX_ARWCK_OE_TIE_SEL_B1, 0,
B1_DQ2_RG_TX_ARWCK_OE_TIE_EN_B1, 1,
B1_DQ2_RG_TX_ARWCKB_OE_TIE_SEL_B1, 0,
B1_DQ2_RG_TX_ARWCKB_OE_TIE_EN_B1, 1,
B1_DQ2_RG_TX_ARDQM_OE_TIE_SEL_B1, 0,
B1_DQ2_RG_TX_ARDQM_OE_TIE_EN_B1, 1,
B1_DQ2_RG_TX_ARDQ_OE_TIE_SEL_B1, 0,
B1_DQ2_RG_TX_ARDQ_OE_TIE_EN_B1, 0xff);
SET32_BITFIELDS(&phy_ao->ca_cmd2,
CA_CMD2_RG_TX_ARCLK_OE_TIE_SEL_CA, 0,
CA_CMD2_RG_TX_ARCLK_OE_TIE_EN_CA, 1,
CA_CMD2_RG_TX_ARCS_OE_TIE_SEL_CA, 0,
CA_CMD2_RG_TX_ARCS_OE_TIE_EN_CA, 1,
CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq13,
SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B0, 0,
SHU_B0_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B0, 1);
SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq13,
SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_SEL_B1, 0,
SHU_B1_DQ13_RG_TX_ARDQSB_OE_TIE_EN_B1, 1);
SET32_BITFIELDS(&phy_ao->shu_ca_cmd13,
SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_SEL_CA, 0,
SHU_CA_CMD13_RG_TX_ARCLKB_OE_TIE_EN_CA, 1);
}
phy_ao = &ch[0].phy_ao;
ph_dly_back = READ32_BITFIELD(&phy_ao->byte[0].shu_b0_dq1,
SHU_B0_DQ1_RG_ARPI_MIDPI_8PH_DLY_B0);
SET32_BITFIELDS(&phy_ao->misc_shu_stbcal,
MISC_SHU_STBCAL_STBCALEN, 0x0,
MISC_SHU_STBCAL_STB_SELPHCALEN, 0x0);
SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dq11,
SHU_B0_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B0, 0);
SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dq11,
SHU_B1_DQ11_RG_RX_ARDQ_RANK_SEL_SER_EN_B1, 0);
SET32_BITFIELDS(&phy_ao->shu_ca_cmd11,
SHU_CA_CMD11_RG_RX_ARCA_RANK_SEL_SER_EN_CA, 0);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
phy_ao = &ch[chn].phy_ao;
SET32_BITFIELDS(&phy_ao->shu_ca_dll1,
SHU_CA_DLL1_RG_ARDLL_PHDET_EN_CA, 0x0,
SHU_CA_DLL1_RG_ARDLL_PHDET_OUT_SEL_CA, 0x0);
SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll1,
SHU_B0_DLL1_RG_ARDLL_PHDET_EN_B0, 0x0,
SHU_B0_DLL1_RG_ARDLL_PHDET_OUT_SEL_B0, 0x0);
SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll1,
SHU_B1_DLL1_RG_ARDLL_PHDET_EN_B1, 0x0,
SHU_B1_DLL1_RG_ARDLL_PHDET_OUT_SEL_B1, 0x0);
}
phy_ao = &ch[0].phy_ao;
SET32_BITFIELDS(&phy_ao->misc_ctrl1, MISC_CTRL1_R_DMDQSIENCG_EN, 0);
SET32_BITFIELDS(&phy_ao->byte[0].shu_b0_dll_arpi2,
SHU_B0_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B0, 0);
SET32_BITFIELDS(&phy_ao->byte[1].shu_b0_dll_arpi2,
SHU_B1_DLL_ARPI2_RG_ARPI_CG_DQSIEN_B1, 0);
SET32_BITFIELDS(&phy_ao->misc_dutyscan1,
MISC_DUTYSCAN1_RX_EYE_SCAN_CG_EN, 1);
SET32_BITFIELDS(&phy_ao->misc_ctrl4, MISC_CTRL4_R_OPT2_CG_DQSIEN, 0);
SET32_BITFIELDS(&phy_ao->misc_stbcal, MISC_STBCAL_DQSIENCG_NORMAL_EN, 0);
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq6,
B0_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B0, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq6,
B1_DQ6_RG_RX_ARDQ_EYE_DLY_DQS_BYPASS_B1, 1);
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 1);
SET32_BITFIELDS(&phy_ao->misc_dutyscan1,
MISC_DUTYSCAN1_EYESCAN_DQS_SYNC_EN, 0x1,
MISC_DUTYSCAN1_EYESCAN_NEW_DQ_SYNC_EN, 0x1,
MISC_DUTYSCAN1_EYESCAN_DQ_SYNC_EN, 0x1);
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq5, B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq5, B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_dq3, B0_DQ3_RG_RX_ARDQ_SMT_EN_B0, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_dq3, B1_DQ3_RG_RX_ARDQ_SMT_EN_B1, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_EN_B0, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_EN_B1, 1);
SET32_BITFIELDS(&phy_ao->misc_jmeter, MISC_JMETER_JMTR_EN, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[0].b0_phy2, B0_PHY2_RG_RX_ARDQS_JM_SEL_B0, 1);
SET32_BITFIELDS(&phy_ao->dvs_b[1].b0_phy2, B1_PHY2_RG_RX_ARDQS_JM_SEL_B1, 1);
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_MIOCK_JIT_EN, 1);
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_RX_EYE_SCAN_EN, 0);
SET32_BITFIELDS(&phy_ao->misc_dutyscan1, MISC_DUTYSCAN1_DQSERRCNT_DIS, 0);
dramc_8_phase_cal_set_best_dly(cali, ph_dly_back);
for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
write32(regs_bak[i].addr, regs_bak[i].value);
}
static void duty_delay_reg_convert(s8 duty_delay, u8 *delay)
{
if (duty_delay < 0)
*delay = -duty_delay;
else if (duty_delay > 0)
*delay = duty_delay + (1 << 5);
else
*delay = 0;
}
static void dramc_duty_set_clk_delay_cell(u8 chn, const s8 *duty_delay)
{
u8 delay;
duty_delay_reg_convert(duty_delay[RANK_0], &delay);
SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_txduty,
SHU_CA_TXDUTY_DA_TX_ARCLK_DUTY_DLY, delay);
}
static void dramc_duty_set_dqs_delay_cell(u8 chn, const s8 *duty_delay)
{
u8 dqs;
u8 delay;
for (dqs = 0; dqs < DQS_NUMBER; dqs++) {
duty_delay_reg_convert(duty_delay[dqs], &delay);
SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
SHU_B0_TXDUTY_DA_TX_ARDQS_DUTY_DLY_B0, delay);
}
}
static void dramc_duty_set_wck_delay_cell(u8 chn, const s8 *duty_delay)
{
u8 dqs;
u8 delay;
for (dqs = 0; dqs < DQS_NUMBER; dqs++) {
duty_delay_reg_convert(duty_delay[dqs], &delay);
SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
SHU_B0_TXDUTY_DA_TX_ARWCK_DUTY_DLY_B0, delay);
}
}
static void dramc_duty_set_dqdqm_delay_cell(u8 chn, const s8 *duty_delay,
u8 k_type)
{
u8 dqs;
u8 delay;
for (dqs = 0; dqs < DQS_NUMBER; dqs++) {
duty_delay_reg_convert(duty_delay[dqs], &delay);
if (k_type == DUTYSCAN_K_DQ)
SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
SHU_B0_TXDUTY_DA_TX_ARDQ_DUTY_DLY_B0, delay);
else if (k_type == DUTYSCAN_K_DQM)
SET32_BITFIELDS(&ch[chn].phy_ao.byte[dqs].shu_b0_txduty,
SHU_B0_TXDUTY_DA_TX_ARDQM_DUTY_DLY_B0, delay);
}
}
void dramc_duty_calibration(const struct sdram_params *params)
{
u32 bc_bak = dramc_get_broadcast();
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
dramc_duty_set_clk_delay_cell(chn, params->duty_clk_delay[chn]);
dramc_duty_set_dqs_delay_cell(chn, params->duty_dqs_delay[chn]);
dramc_duty_set_wck_delay_cell(chn, params->duty_wck_delay[chn]);
dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dqm_delay[chn],
DUTYSCAN_K_DQM);
dramc_duty_set_dqdqm_delay_cell(chn, params->duty_dq_delay[chn],
DUTYSCAN_K_DQ);
}
dramc_set_broadcast(bc_bak);
}

392
src/soc/mediatek/mt8192/dramc_pi_main.c
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@ -1,392 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/dramc_pi_api.h>
#include <soc/dramc_register.h>
#include <soc/pll.h>
#include <soc/pll_common.h>
#include <soc/regulator.h>
static void dramc_write_shift_mck_write_dbi(const struct ddr_cali *cali, s8 shift_value)
{
u8 div_shift;
s8 ui_move;
div_shift = get_mck2ui_div_shift(cali);
ui_move = shift_value * (1 << div_shift);
shift_dq_ui(cali, cali->rank, ui_move);
}
static void dramc_ac_timing_optimize(const struct ddr_cali *cali)
{
u8 rf_group, cab_id;
u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt;
enum {
TRFCAB_130,
TRFCAB_180,
TRFCAB_280,
TRFCAB_380,
TRFCAB_NUM,
};
enum {
GRP_DDR800_DIV4_ACTIM,
GRP_DDR1200_ACTIM,
GRP_DDR1600_ACTIM,
GRP_DDR1866_ACTIM,
GRP_DDR2400_ACTIM,
GRP_DDR3200_ACTIM,
GRP_DDR4266_ACTIM,
GRP_ACTIM_NUM,
};
struct optimize_ac_time {
u8 trfc;
u8 trfc_05t;
u8 trfc_pb;
u8 trfrc_pb05t;
u16 tx_ref_cnt;
};
const u8 density = cali->density;
const dram_freq_grp freq_group = get_freq_group(cali);
/* tRFCab */
struct optimize_ac_time *ptr_trfcab_opt;
struct optimize_ac_time trfcab_opt[GRP_ACTIM_NUM][TRFCAB_NUM] = {
[GRP_DDR800_DIV4_ACTIM] = {
{.trfc = 14, .trfc_05t = 0, .trfc_pb = 0,
.trfrc_pb05t = 0, .tx_ref_cnt = 28},
{.trfc = 24, .trfc_05t = 0, .trfc_pb = 6,
.trfrc_pb05t = 0, .tx_ref_cnt = 38},
{.trfc = 44, .trfc_05t = 0, .trfc_pb = 16,
.trfrc_pb05t = 0, .tx_ref_cnt = 58},
{.trfc = 64, .trfc_05t = 0, .trfc_pb = 26,
.trfrc_pb05t = 0, .tx_ref_cnt = 78}
},
[GRP_DDR1200_ACTIM] = {
{.trfc = 8, .trfc_05t = 0, .trfc_pb = 0,
.trfrc_pb05t = 0, .tx_ref_cnt = 21},
{.trfc = 15, .trfc_05t = 1, .trfc_pb = 2,
.trfrc_pb05t = 0, .tx_ref_cnt = 29},
{.trfc = 30, .trfc_05t = 1, .trfc_pb = 9,
.trfrc_pb05t = 1, .tx_ref_cnt = 44},
{.trfc = 45, .trfc_05t = 1, .trfc_pb = 17,
.trfrc_pb05t = 0, .tx_ref_cnt = 59}
},
[GRP_DDR1600_ACTIM] = {
{.trfc = 14, .trfc_05t = 0, .trfc_pb = 0,
.trfrc_pb05t = 0, .tx_ref_cnt = 28},
{.trfc = 24, .trfc_05t = 0, .trfc_pb = 6,
.trfrc_pb05t = 0, .tx_ref_cnt = 38},
{.trfc = 44, .trfc_05t = 0, .trfc_pb = 16,
.trfrc_pb05t = 0, .tx_ref_cnt = 58},
{.trfc = 64, .trfc_05t = 0, .trfc_pb = 26,
.trfrc_pb05t = 0, .tx_ref_cnt = 78}
},
[GRP_DDR1866_ACTIM] = {
{.trfc = 18, .trfc_05t = 1, .trfc_pb = 2,
.trfrc_pb05t = 0, .tx_ref_cnt = 33},
{.trfc = 30, .trfc_05t = 0, .trfc_pb = 9,
.trfrc_pb05t = 0, .tx_ref_cnt = 44},
{.trfc = 53, .trfc_05t = 1, .trfc_pb = 21,
.trfrc_pb05t = 0, .tx_ref_cnt = 68},
{.trfc = 77, .trfc_05t = 0, .trfc_pb = 32,
.trfrc_pb05t = 1, .tx_ref_cnt = 91}
},
[GRP_DDR2400_ACTIM] = {
{.trfc = 27, .trfc_05t = 1, .trfc_pb = 6,
.trfrc_pb05t = 1, .tx_ref_cnt = 42},
{.trfc = 42, .trfc_05t = 1, .trfc_pb = 15,
.trfrc_pb05t = 1, .tx_ref_cnt = 57},
{.trfc = 72, .trfc_05t = 1, .trfc_pb = 30,
.trfrc_pb05t = 1, .tx_ref_cnt = 87},
{.trfc = 102, .trfc_05t = 1, .trfc_pb = 45,
.trfrc_pb05t = 1, .tx_ref_cnt = 117}
},
[GRP_DDR3200_ACTIM] = {
{.trfc = 40, .trfc_05t = 0, .trfc_pb = 12,
.trfrc_pb05t = 0, .tx_ref_cnt = 55},
{.trfc = 60, .trfc_05t = 0, .trfc_pb = 24,
.trfrc_pb05t = 0, .tx_ref_cnt = 75},
{.trfc = 100, .trfc_05t = 0, .trfc_pb = 44,
.trfrc_pb05t = 0, .tx_ref_cnt = 115},
{.trfc = 140, .trfc_05t = 0, .trfc_pb = 64,
.trfrc_pb05t = 0, .tx_ref_cnt = 155}
},
[GRP_DDR4266_ACTIM] = {
{.trfc = 57, .trfc_05t = 1, .trfc_pb = 20,
.trfrc_pb05t = 0, .tx_ref_cnt = 74},
{.trfc = 84, .trfc_05t = 0, .trfc_pb = 36,
.trfrc_pb05t = 0, .tx_ref_cnt = 100},
{.trfc = 137, .trfc_05t = 1, .trfc_pb = 63,
.trfrc_pb05t = 0, .tx_ref_cnt = 154},
{.trfc = 191, .trfc_05t = 0, .trfc_pb = 89,
.trfrc_pb05t = 1, .tx_ref_cnt = 207}
}
};
switch (density) {
case 0x0:
rf_group = TRFCAB_130;
break;
case 0x1:
case 0x2:
rf_group = TRFCAB_180;
break;
case 0x3:
case 0x4:
rf_group = TRFCAB_280;
break;
case 0x5:
case 0x6:
rf_group = TRFCAB_380;
break;
default:
die("Invalid DDR density %u\n", density);
return;
}
switch (freq_group) {
case DDRFREQ_400:
cab_id = GRP_DDR800_DIV4_ACTIM;
break;
case DDRFREQ_600:
cab_id = GRP_DDR1200_ACTIM;
break;
case DDRFREQ_800:
cab_id = GRP_DDR1600_ACTIM;
break;
case DDRFREQ_933:
cab_id = GRP_DDR1866_ACTIM;
break;
case DDRFREQ_1200:
cab_id = GRP_DDR2400_ACTIM;
break;
case DDRFREQ_1600:
cab_id = GRP_DDR3200_ACTIM;
break;
case DDRFREQ_2133:
cab_id = GRP_DDR4266_ACTIM;
break;
default:
die("Invalid DDR frequency group %u\n", freq_group);
return;
}
ptr_trfcab_opt = &trfcab_opt[cab_id][0];
trfc = ptr_trfcab_opt[rf_group].trfc;
trfc_05t = ptr_trfcab_opt[rf_group].trfc_05t;
trfc_pb = ptr_trfcab_opt[rf_group].trfc_pb;
trfrc_pb05t = ptr_trfcab_opt[rf_group].trfrc_pb05t;
tx_ref_cnt = ptr_trfcab_opt[rf_group].tx_ref_cnt;
for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
SHU_ACTIM3_TRFC, trfc);
SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
SHU_AC_TIME_05T_TRFC_05T, trfc_05t);
SET32_BITFIELDS(&ch[chn].ao.shu_actim4,
SHU_ACTIM4_TXREFCNT, tx_ref_cnt);
SET32_BITFIELDS(&ch[chn].ao.shu_actim3,
SHU_ACTIM3_TRFCPB, trfc_pb);
SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t,
SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t);
dramc_dbg("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, "
"TRFCpb %u, TRFCpb_05T %u\n",
density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t);
}
}
static void set_vcore_voltage(const struct ddr_cali *cali)
{
u32 vcore = get_vcore_value(cali);
dramc_info("Set DRAM vcore voltage to %u\n", vcore);
mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore);
}
static void get_dram_info_after_cal(struct ddr_cali *cali)
{
u8 vendor_id, density, max_density = 0;
u32 size_gb, max_size = 0;
vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff;
dramc_info("Vendor id is %#x\n", vendor_id);
for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) {
density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff;
dramc_dbg("MR8 %#x\n", density);
density = (density >> 2) & 0xf;
switch (density) {
/* these case values are from JESD209-4C MR8 Density OP[5:2] */
case 0x0:
size_gb = 4;
break;
case 0x1:
size_gb = 6;
break;
case 0x2:
size_gb = 8;
break;
case 0x3:
size_gb = 12;
break;
case 0x4:
size_gb = 16;
break;
case 0x5:
size_gb = 24;
break;
case 0x6:
size_gb = 32;
break;
case 0xC:
size_gb = 2;
break;
default:
dramc_err("Unexpected mode register density value: %#x\n", density);
size_gb = 0;
break;
}
if (size_gb > max_size) {
max_size = size_gb;
max_density = density;
}
dramc_dbg("RK%u size %uGb, density:%u\n", rk, size_gb, max_density);
}
cali->density = max_density;
}
static void dramc_calibration_single_channel(struct ddr_cali *cali, u8 chn)
{
cali->chn = chn;
SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 0,
CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 1,
CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
}
static void dramc_calibration_all_channels(struct ddr_cali *cali)
{
u8 chn_bak, rank_bak;
const dbi_mode w_dbi = get_write_dbi(cali);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
SET32_BITFIELDS(&ch[chn].phy_ao.ca_cmd2,
CA_CMD2_RG_TX_ARCMD_OE_DIS_CA, 1,
CA_CMD2_RG_TX_ARCA_OE_TIE_SEL_CA, 0,
CA_CMD2_RG_TX_ARCA_OE_TIE_EN_CA, 0xff);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
dramc_calibration_single_channel(cali, chn);
if (w_dbi == DBI_ON) {
chn_bak = cali->chn;
rank_bak = cali->rank;
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
for (u8 rank = RANK_0; rank < RANK_MAX; rank++) {
cali->chn = chn;
cali->rank = rank;
dramc_write_shift_mck_write_dbi(cali, -1);
}
cali->chn = chn_bak;
cali->rank = rank_bak;
apply_write_dbi_power_improve(true);
}
dramc_write_dbi_onoff(w_dbi);
tx_picg_setting(cali);
if (cali->support_ranks == DUAL_RANK_DDR)
xrtrtr_shu_setting(cali);
freq_jump_ratio_calculation(cali);
dramc_hmr4_presetting(cali);
dramc_enable_perbank_refresh(true);
dramc_modified_refresh_mode();
dramc_cke_debounce(cali);
for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
dramc_hw_dqsosc(cali, chn);
}
static void mem_pll_init(void)
{
SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_POWER_ISO_ENABLE, 3);
udelay(30);
SET32_BITFIELDS(&mtk_apmixed->mpll_con3, PLL_ISO_ENABLE, 0);
udelay(1);
SET32_BITFIELDS(&mtk_apmixed->mpll_con1, PLL_CON1, MPLL_CON1_FREQ);
SET32_BITFIELDS(&mtk_apmixed->mpll_con0, PLL_ENABLE, 1);
udelay(20);
SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_IOS_SEL, 0);
SET32_BITFIELDS(&mtk_apmixed->pllon_con0, MPLL_EN_SEL, 0);
SET32_BITFIELDS(&mtk_apmixed->pllon_con1, MPLL_PWR_SEL, 0);
SET32_BITFIELDS(&mtk_apmixed->pllon_con2, MPLL_BY_ISO_DLY, 0);
SET32_BITFIELDS(&mtk_apmixed->pllon_con3, MPLL_BY_PWR_DLY, 0);
}
void init_dram(const struct dramc_data *dparam)
{
u32 bc_bak;
u8 k_shuffle, k_shuffle_end;
u8 pll_mode = 0;
bool first_freq_k = true;
struct ddr_cali cali = {0};
struct mr_values mr_value;
const struct ddr_base_info *ddr_info = &dparam->ddr_info;
cali.pll_mode = &pll_mode;
cali.mr_value = &mr_value;
cali.support_ranks = ddr_info->support_ranks;
cali.cbt_mode[RANK_0] = ddr_info->cbt_mode[RANK_0];
cali.cbt_mode[RANK_1] = ddr_info->cbt_mode[RANK_1];
cali.emi_config = &ddr_info->emi_config;
dramc_set_broadcast(DRAMC_BROADCAST_ON);
mem_pll_init();
global_option_init(&cali);
bc_bak = dramc_get_broadcast();
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
emi_mdl_init(cali.emi_config);
dramc_set_broadcast(bc_bak);
dramc_sw_impedance_cal(ODT_OFF, &cali.impedance);
dramc_sw_impedance_cal(ODT_ON, &cali.impedance);
if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS)
k_shuffle_end = CALI_SEQ_MAX;
else
k_shuffle_end = CALI_SEQ1;
for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) {
set_cali_datas(&cali, dparam, k_shuffle);
set_vcore_voltage(&cali);
dfs_init_for_calibration(&cali);
if (first_freq_k)
emi_init2();
dramc_calibration_all_channels(&cali);
/* only need to do once to get DDR's base information */
if (first_freq_k)
get_dram_info_after_cal(&cali);
dramc_ac_timing_optimize(&cali);
dramc_save_result_to_shuffle(DRAM_DFS_SHU0, cali.shu);
/* for frequency switch in dramc_mode_reg_init phase */
if (first_freq_k)
dramc_load_shuffle_to_dramc(cali.shu, DRAM_DFS_SHU1);
first_freq_k = false;
dramc_info("Calibration of data rate %u finished\n", get_frequency(&cali) * 2);
}
}

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@ -1,167 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/dramc_pi_api.h>
#include <soc/dramc_register.h>
#include <soc/infracfg.h>
struct dfs_frequency_table {
u32 frequency;
dram_freq_grp freq_group;
dram_div_mode div_mode;
dram_dfs_shu shuffle_saved;
vref_cali_mode vref_cali;
u32 vcore;
};
static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = {
[CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000},
[CALI_SEQ1] = {1200, DDRFREQ_1200, DIV8_MODE, DRAM_DFS_SHU2, VREF_CALI_ON, 662500},
[CALI_SEQ2] = {600, DDRFREQ_600, DIV8_MODE, DRAM_DFS_SHU5, VREF_CALI_OFF, 650000},
[CALI_SEQ3] = {933, DDRFREQ_933, DIV8_MODE, DRAM_DFS_SHU3, VREF_CALI_OFF, 662500},
[CALI_SEQ4] = {400, DDRFREQ_400, DIV4_MODE, DRAM_DFS_SHU6, VREF_CALI_OFF, 650000},
[CALI_SEQ5] = {2133, DDRFREQ_2133, DIV8_MODE, DRAM_DFS_SHU0, VREF_CALI_ON, 725000},
[CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500},
};
void dramc_set_broadcast(u32 onoff)
{
write32(&mt8192_infracfg->dramc_wbr, onoff);
}
u32 dramc_get_broadcast(void)
{
return read32(&mt8192_infracfg->dramc_wbr);
}
u8 get_fsp(const struct ddr_cali *cali)
{
return cali->fsp;
}
dram_div_mode get_div_mode(const struct ddr_cali *cali)
{
return cali->div_mode;
}
dram_freq_grp get_freq_group(const struct ddr_cali *cali)
{
return cali->freq_group;
}
dbi_mode get_write_dbi(const struct ddr_cali *cali)
{
return cali->w_dbi[get_fsp(cali)];
}
dram_odt_state get_odt_state(const struct ddr_cali *cali)
{
return cali->odt_onoff;
}
dram_dfs_shu get_shu(const struct ddr_cali *cali)
{
return cali->shu;
}
dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali)
{
return cali->cbt_mode[cali->rank];
}
u32 get_vcore_value(const struct ddr_cali *cali)
{
return cali->vcore_voltage;
}
u32 get_frequency(const struct ddr_cali *cali)
{
return cali->frequency;
}
vref_cali_mode get_vref_cali(const struct ddr_cali *cali)
{
return cali->vref_cali;
}
dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali)
{
return cali->pinmux_type;
}
u8 get_mck2ui_div_shift(const struct ddr_cali *cali)
{
if (get_div_mode(cali) == DIV4_MODE)
return 2;
else
return 3;
}
dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu)
{
return freq_shuffle_table[k_shu].shuffle_saved;
}
dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu)
{
for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++)
if (freq_shuffle_table[k_shu].shuffle_saved == shu)
return freq_shuffle_table[k_shu].freq_group;
dramc_err("Invalid shuffle: %d\n", shu);
return DDRFREQ_800;
}
u32 get_frequency_by_shu(dram_dfs_shu shu)
{
for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++)
if (freq_shuffle_table[k_shu].shuffle_saved == shu)
return freq_shuffle_table[k_shu].frequency;
dramc_err("Invalid shuffle: %d, using k_shu = %d\n", shu, CALI_SEQ0);
return freq_shuffle_table[CALI_SEQ0].frequency;
}
dram_freq_grp get_highest_freq_group(void)
{
dram_freq_grp highest_freq = DDRFREQ_800;
for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++)
if (freq_shuffle_table[k_shu].freq_group > highest_freq)
highest_freq = freq_shuffle_table[k_shu].freq_group;
dramc_dbg("Highest freq is: %d\n", highest_freq);
return highest_freq;
}
void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu)
{
const struct dfs_frequency_table *shuffle = &freq_shuffle_table[k_shu];
cali->chn = CHANNEL_A;
cali->rank = RANK_0;
cali->fsp = (shuffle->freq_group < DDRFREQ_1600) ? FSP_0 : FSP_1;
cali->w_dbi[FSP_0] = DBI_OFF;
cali->w_dbi[FSP_1] = DBI_ON;
cali->frequency = shuffle->frequency;
cali->freq_group = shuffle->freq_group;
cali->div_mode = shuffle->div_mode;
cali->shu = shuffle->shuffle_saved;
cali->vref_cali = shuffle->vref_cali;
cali->vcore_voltage = shuffle->vcore;
cali->odt_onoff = (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON;
cali->params = &dparam->freq_params[cali->shu];
dramc_dbg("cali data (size: %ld) fsp: %d, freq_group: %d, div_mode: %d, "
"shu: %d, vref_cali: %d, odt_onoff: %d, vcore: %d\n",
sizeof(*cali), cali->fsp, cali->freq_group, cali->div_mode, cali->shu,
cali->vref_cali, cali->odt_onoff, cali->vcore_voltage);
}
void dramc_auto_refresh_switch(u8 chn, bool enable)
{
SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, enable ? 0 : 1);
if (!enable)
udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa,
MISC_STATUSA_REFRESH_QUEUE_CNT));
}

440
src/soc/mediatek/mt8192/emi.c
View File

@ -1,440 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/dramc_pi_api.h>
#include <soc/dramc_register.h>
#include <soc/infracfg.h>
#include <symbols.h>
static struct emi_regs *emi_reg = (void *)EMI_BASE;
static struct emi_mpu_regs *const emi_mpu = (void *)EMI_MPU_BASE;
static struct infra_ao_mem_regs *infra_ao_mem = (void *)INFRACFG_AO_MEM_BASE;
static void emi_center_config(void)
{
/* set EMI default settings which EMI hardware needs */
write32(&emi_reg->cona, 0xf053f154);
write32(&emi_reg->conp, 0x182e2d33);
write32(&emi_reg->conb, 0x0f251025);
write32(&emi_reg->conq, 0x122a1027);
write32(&emi_reg->conc, 0x1a31162d);
write32(&emi_reg->conb_2nd, 0x182e2d33);
write32(&emi_reg->conc_2nd, 0x0f251025);
write32(&emi_reg->conp_2nd, 0x122a1027);
write32(&emi_reg->conq_2nd, 0x1a31162d);
write32(&emi_reg->conb_3rd, 0x1024202c);
write32(&emi_reg->conc_3rd, 0x0b210c21);
write32(&emi_reg->conp_3rd, 0x0f250d23);
write32(&emi_reg->conq_3rd, 0x152b1228);
write32(&emi_reg->conb_4th, 0x0c201a28);
write32(&emi_reg->conc_4th, 0x0d230a20);
write32(&emi_reg->conp_4th, 0x0e260d24);
write32(&emi_reg->conq_4th, 0x132d1229);
write32(&emi_reg->conb_5th, 0x0c201a28);
write32(&emi_reg->conc_5th, 0x0d230a20);
write32(&emi_reg->conp_5th, 0x0e260d24);
write32(&emi_reg->conq_5th, 0x132d1229);
write32(&emi_reg->conb_6th, 0x0c201a28);
write32(&emi_reg->conc_6th, 0x0d230a20);
write32(&emi_reg->conp_6th, 0x0e260d24);
write32(&emi_reg->conq_6th, 0x132d1229);
write32(&emi_reg->conb_7th, 0x0e290e28);
write32(&emi_reg->conc_7th, 0x091e1322);
write32(&emi_reg->mpud26_st, 0x0f29112a);
write32(&emi_reg->conq_7th, 0x0c240a1f);
write32(&emi_reg->conb_8th, 0x0e290e28);
write32(&emi_reg->conc_8th, 0x091e1322);
write32(&emi_reg->conp_8th, 0x0f29112a);
write32(&emi_reg->conq_8th, 0x0c240a1f);
write32(&emi_reg->cong, 0x37373a57);
write32(&emi_reg->conr, 0x3f3f3c39);
write32(&emi_reg->cong_2nd, 0x3836374e);
write32(&emi_reg->conr_2nd, 0x41413d3a);
write32(&emi_reg->cong_3rd, 0x33313241);
write32(&emi_reg->conr_3rd, 0x3a3a3835);
write32(&emi_reg->cong_4th, 0x34343542);
write32(&emi_reg->conr_4th, 0x3b3b3835);
write32(&emi_reg->cong_5th, 0x34343542);
write32(&emi_reg->conr_5th, 0x3b3b3835);
write32(&emi_reg->cong_6th, 0x34343542);
write32(&emi_reg->conr_6th, 0x3b3b3835);
write32(&emi_reg->cong_7th, 0x37333034);
write32(&emi_reg->conr_7th, 0x39393a39);
write32(&emi_reg->cong_8th, 0x37333034);
write32(&emi_reg->conr_8th, 0x39393a39);
write32(&emi_reg->cond, 0x3657587a);
write32(&emi_reg->cone, 0x0000c042);
write32(&emi_reg->conf, 0x08421000);
write32(&emi_reg->conh, 0x00000083);
write32(&emi_reg->conh_2nd, 0x00073210);
write32(&emi_reg->coni, 0x00008802);
write32(&emi_reg->conj, 0x00000000);
write32(&emi_reg->conm, 0x007812ff);
write32(&emi_reg->conn, 0x00000000);
write32(&emi_reg->mdct, 0x11120c1f);
write32(&emi_reg->shf0, 0x11120c1f);
write32(&emi_reg->mdct_2nd, 0x00001123);
write32(&emi_reg->shf1, 0x00001123);
write32(&emi_reg->iocl, 0xa8a8a8a8);
write32(&emi_reg->iocl_2nd, 0x25252525);
write32(&emi_reg->iocm, 0xa8a8a8a8);
write32(&emi_reg->iocm_2nd, 0x25252525);
write32(&emi_reg->testb, 0x00060037);
write32(&emi_reg->testc, 0x384a0014);
write32(&emi_reg->testd, 0xa0000000);
write32(&emi_reg->arba, 0x20107244);
write32(&emi_reg->arbb, 0x10107044);
write32(&emi_reg->arbc, 0x343450df);
write32(&emi_reg->arbd, 0x0000f0d0);
write32(&emi_reg->arbe, 0x10106048);
write32(&emi_reg->arbf, 0x343450df);
write32(&emi_reg->arbg, 0x83837044);
write32(&emi_reg->arbh, 0x83837044);
write32(&emi_reg->arbi, 0x00007108);
write32(&emi_reg->arbi_2nd, 0x00007108);
write32(&emi_reg->arbk, 0x090a4000);
write32(&emi_reg->slct, 0xff0bff00);
write32(&emi_reg->bmen, 0x00ff0001);
write32(&emi_reg->clua, 0x10000008);
write32(&emi_reg->slva, 0xffffffff);
write32(&emi_reg->thro_os0, 0x24240101);
write32(&emi_reg->thro_os1, 0x01012424);
write32(&emi_reg->thro_os2, 0x50500101);
write32(&emi_reg->thro_os3, 0x01015050);
write32(&emi_reg->thro_ctrl0, 0x0fc39a30);
write32(&emi_reg->thro_prd0, 0x05050003);
write32(&emi_reg->thro_prd1, 0x254dffff);
write32(&emi_reg->thro_lat0, 0x465a788c);
write32(&emi_reg->thro_lat1, 0x000003e8);
write32(&emi_reg->thro_lat2, 0x0000036b);
write32(&emi_reg->thro_lat3, 0x00000290);
write32(&emi_reg->thro_lat4, 0x00000200);
write32(&emi_reg->thro_lat5, 0x00000000);
write32(&emi_reg->thro_lat6, 0x00000000);
write32(&emi_reg->thro_ctrl1, 0x02531cff);
write32(&emi_reg->thro_prd2, 0x00002785);
write32(&emi_reg->thro_lat7, 0x000001b5);
write32(&emi_reg->thro_lat8, 0x003c0000);
write32(&emi_reg->thro_prd3, 0x0255250d);
write32(&emi_reg->bwlmta, 0xffff3c59);
write32(&emi_reg->bwlmtb, 0xffff00ff);
write32(&emi_reg->bwlmte, 0xffffffff);
write32(&emi_reg->bwlmtf, 0x0000ffff);
write32(&emi_reg->thro_lat9, 0x0000014b);
write32(&emi_reg->thro_lat10, 0x002d0000);
write32(&emi_reg->thro_lat11, 0x00000185);
write32(&emi_reg->thro_lat12, 0x003c0000);
write32(&emi_reg->thro_lat13, 0x00000185);
write32(&emi_reg->thro_lat14, 0x003c0000);
write32(&emi_reg->bwlmte_2nd, 0xffffffff);
write32(&emi_reg->bwlmtf_2nd, 0xffffffff);
write32(&emi_reg->bwlmtg_2nd, 0xffffffff);
write32(&emi_reg->bwlmte_4th, 0xffffffff);
write32(&emi_reg->bwlmtf_4th, 0x0000ffff);
write32(&emi_reg->bwlmte_5th, 0xffffffff);
write32(&emi_reg->bwlmtf_5th, 0xffffffff);
write32(&emi_reg->bwlmtg_5th, 0xffffffff);
write32(&emi_reg->thro_lat27, 0x41547082);
write32(&emi_reg->thro_lat28, 0x38382a38);
write32(&emi_reg->thro_lat29, 0x000001d4);
write32(&emi_reg->thro_lat30, 0x00000190);
write32(&emi_reg->thro_lat31, 0x0000012c);
write32(&emi_reg->thro_lat32, 0x000000ed);
write32(&emi_reg->thro_lat33, 0x000000c8);
write32(&emi_reg->thro_lat34, 0x00000096);
write32(&emi_reg->thro_lat35, 0x000000c8);
write32(&emi_reg->thro_lat36, 0x000000c8);
write32(&emi_reg->thro_lat41, 0x26304048);
write32(&emi_reg->thro_lat42, 0x20201820);
write32(&emi_reg->thro_lat55, 0x181e282f);
write32(&emi_reg->thro_lat56, 0x14140f18);
write32(&emi_reg->thro_lat69, 0x7496c8ea);
write32(&emi_reg->thro_lat70, 0x64644b64);
write32(&emi_reg->thro_lat83, 0x01010101);
write32(&emi_reg->thro_lat84, 0x01010101);
write32(&emi_reg->thro_lat97, 0x7496c8ea);
write32(&emi_reg->thro_lat98, 0x64644b64);
write32(&emi_reg->thro_lat111, 0x01010101);
write32(&emi_reg->thro_lat112, 0x01010101);
write32(&emi_reg->thro_prd5, 0x300ff025);
write32(&emi_reg->thro_lat113, 0x000003e8);
write32(&emi_reg->thro_lat114, 0x0000036b);
write32(&emi_reg->thro_lat115, 0x00000290);
write32(&emi_reg->thro_lat116, 0x00000200);
write32(&emi_reg->thro_lat117, 0x000001b5);
write32(&emi_reg->thro_lat118, 0x0000014b);
write32(&emi_reg->thro_lat119, 0x00000185);
write32(&emi_reg->thro_lat120, 0x00000185);
write32(&emi_reg->thro_lat125, 0x52698ca0);
write32(&emi_reg->thro_lat126, 0x46463546);
write32(&emi_reg->thro_lat139, 0x01010101);
write32(&emi_reg->thro_lat140, 0x01010101);
write32(&emi_reg->qos_mdr_be0a, 0x00000009);
write32(&emi_reg->qos_mdr_be1a, 0x00000000);
write32(&emi_reg->qos_mdr_shf0, 0x00730000);
write32(&emi_reg->qos_mdr_shf1, 0x00000808);
write32(&emi_reg->qos_mdw_be0a, 0x00000028);
write32(&emi_reg->qos_mdw_be1a, 0x00000000);
write32(&emi_reg->qos_mdw_shf0, 0x00730000);
write32(&emi_reg->qos_mdw_shf1, 0x00000808);
write32(&emi_reg->qos_apr_be0a, 0x00000080);
write32(&emi_reg->qos_apr_be1a, 0x00000000);
write32(&emi_reg->qos_apr_shf0, 0x30201008);
write32(&emi_reg->qos_apw_be0a, 0x00000800);
write32(&emi_reg->qos_apw_be1a, 0x00000000);
write32(&emi_reg->qos_mmr_be0a, 0x00008000);
write32(&emi_reg->qos_mmr_be1a, 0x00020000);
write32(&emi_reg->qos_mmr_be1b, 0x00001000);
write32(&emi_reg->qos_mmr_be2a, 0x00010000);
write32(&emi_reg->qos_mmr_be2b, 0x00000800);
write32(&emi_reg->qos_mmr_shf0, 0x08080000);
write32(&emi_reg->qos_mmr_shf1, 0x00073030);
write32(&emi_reg->qos_mmw_be0a, 0x00040000);
write32(&emi_reg->qos_mmw_be1a, 0x00100000);
write32(&emi_reg->qos_mmw_be1b, 0x00004000);
write32(&emi_reg->qos_mmw_be2a, 0x00080000);
write32(&emi_reg->qos_mmw_be2b, 0x00002000);
write32(&emi_reg->qos_mmw_shf0, 0x08080000);
write32(&emi_reg->qos_mmw_shf1, 0x00074040);
write32(&emi_reg->qos_mdhwr_be0a, 0x00400000);
write32(&emi_reg->qos_mdhwr_be1a, 0x00200000);
write32(&emi_reg->qos_mdhwr_shf0, 0x10100404);
write32(&emi_reg->qos_mdhww_be0a, 0x01000000);
write32(&emi_reg->qos_mdhww_be1a, 0x00800000);
write32(&emi_reg->qos_gpur_be0a, 0x04000000);
write32(&emi_reg->qos_gpur_be1a, 0x02000000);
write32(&emi_reg->qos_gpur_shf0, 0x60602010);
write32(&emi_reg->qos_gpuw_be0a, 0x10000000);
write32(&emi_reg->qos_gpuw_be1a, 0x08000000);
write32(&emi_reg->qos_arbr_be0a, 0x00000009);
write32(&emi_reg->qos_arbr_be1a, 0x04400080);
write32(&emi_reg->qos_arbr_shf0, 0x0f170f11);
write32(&emi_reg->qos_ctrl1, 0x0303f7f7);
write32(&emi_reg->ext_lt_con1_1st, 0x00000166);
write32(&emi_reg->ext_lt_con2_1st, 0xffffffff);
write32(&emi_reg->ext_lt_con3_1st, 0xffffffff);
write32(&emi_reg->ext_lt_con1_2nd, 0x00400166);
write32(&emi_reg->ext_lt_con2_2nd, 0xffffffff);
write32(&emi_reg->ext_lt_con3_2nd, 0xffffffff);
write32(&emi_reg->ext_lt_con1_3rd, 0x00000266);
write32(&emi_reg->ext_lt_con2_3rd, 0xffffffff);
write32(&emi_reg->ext_lt_con3_3rd, 0xffffffff);
write32(&emi_reg->ext_lt_con1_4th, 0x00400266);
write32(&emi_reg->ext_lt_con2_4th, 0xffffffff);
write32(&emi_reg->ext_lt_con3_4th, 0xffffffff);
write32(&emi_reg->prtcl_m0_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m0_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m0_msk, 0xffffffff);
write32(&emi_reg->prtcl_m1_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m1_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m1_msk, 0xffffffff);
write32(&emi_reg->prtcl_m2_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m2_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m2_msk, 0xffffffff);
write32(&emi_reg->prtcl_m3_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m3_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m3_msk, 0xffffffff);
write32(&emi_reg->prtcl_m4_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m4_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m4_msk, 0xffffffff);
write32(&emi_reg->prtcl_m5_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m5_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m5_msk, 0xffffffff);
write32(&emi_reg->prtcl_m6_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m6_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m6_msk, 0xffffffff);
write32(&emi_reg->prtcl_m7_cyc, 0xffffffff);
write32(&emi_reg->prtcl_m7_ctl, 0x001ffc85);
write32(&emi_reg->prtcl_m7_msk, 0xffffffff);
write32(&emi_reg->dvfs_shf_con, 0x00000000);
write32(&emi_reg->mxto0, 0x60606060);
write32(&emi_reg->mxto1, 0x60606060);
write32(&emi_reg->conk, 0x00000000);
write32(&emi_reg->thro_slv_con0, 0x08ffbbff);
write32(&emi_reg->thro_slv_con1, 0xffff5b3c);
write32(&emi_reg->bwlmte_8th, 0xffff00ff);
write32(&emi_reg->bwlmtf_8th, 0x00ffffff);
write32(&emi_reg->bwlmtg_8th, 0xffff00ff);
write32(&emi_reg->bwlmth_8th, 0x00ffffff);
write32(&emi_reg->bwlmtg_7th, 0x00000000);
write32(&emi_reg->chn_hash0, 0xC0000000);
}
static void emi_chn_config(void)
{
struct emi_chn_regs *emi_chn = &ch->emi_chn;
/* set EMI channel default settings which EMI hardware needs */
write32(&emi_chn->cona, 0x0400f051);
write32(&emi_chn->conb, 0x00ff6048);
write32(&emi_chn->conc, 0x00000004);
write32(&emi_chn->mdct, 0x99f08c03);
write32(&emi_chn->shf0, 0x9a508c17);
write32(&emi_chn->testb, 0x00038137);
write32(&emi_chn->testc, 0x38460002);
write32(&emi_chn->testd, 0x00000000);
write32(&emi_chn->ap_early_cke, 0x000002ff);
write32(&emi_chn->dqfr, 0x00003111);
write32(&emi_chn->arbi, 0x22607188);
write32(&emi_chn->arbi_2nd, 0x22607188);
write32(&emi_chn->arbj, 0x3719595e);
write32(&emi_chn->arbj_2nd, 0x2719595e);
write32(&emi_chn->arbk, 0x64f3ff79);
write32(&emi_chn->arbk_2nd, 0x64f3ff79);
write32(&emi_chn->slct, 0x011b0868);
write32(&emi_chn->arb_rff, 0xa7414222);
write32(&emi_chn->drs_mon0, 0x0000f801);
write32(&emi_chn->drs_mon1, 0x40000000);
write32(&emi_chn->rkarb0, 0x000c802f);
write32(&emi_chn->rkarb1, 0xbd3f3f7e);
write32(&emi_chn->rkarb2, 0x7e003d7e);
write32(&emi_chn->eco3, 0x00000000);
write32(&emi_chn->md_pre_mask, 0xaa0148ff);
write32(&emi_chn->md_pre_mask_shf, 0xaa6168ff);
write32(&emi_chn->md_pre_mask_shf0, 0xaa516cff);
write32(&emi_chn->md_pre_mask_shf1, 0xaa0140ff);
write32(&emi_chn->qos_mdr_shf0, 0x9f658633);
}
static void emi_init(void)
{
dramc_set_broadcast(DRAMC_BROADCAST_ON);
emi_center_config();
emi_chn_config();
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
}
void emi_mdl_init(const struct emi_mdl *emi_con)
{
emi_init();
write32(&emi_reg->cona, emi_con->cona_val);
write32(&emi_reg->conf, emi_con->conf_val);
write32(&emi_reg->conh, emi_con->conh_val);
for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++)
write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val);
}
u32 get_column_num(void)
{
u32 ma_type = read32(&emi_reg->cona);
u32 ma_type_r0 = ((ma_type >> 20) & 0x3) + 1;
u32 ma_type_r1 = ((ma_type >> 22) & 0x3) + 1;
ma_type = MIN(ma_type_r0, ma_type_r1);
return ma_type;
}
static void emi_sw_setting(void)
{
setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4));
setbits32(&emi_mpu->mpu_ctrl_d[7], BIT(4));
/* set EMI default bandwidth threshold */
write32(&emi_reg->bwct0, 0x05008305);
write32(&emi_reg->bwct0_6th, 0x08ff8705);
write32(&emi_reg->bwct0_3rd, 0x0dff8a05);
setbits32(&emi_reg->thro_ctrl1, 0x3 << 8);
}
static void dramc_dcm_setting(void)
{
/* set EMI dcm default settgings */
write32(&infra_ao_mem->emi_idle_bit_en_0, 0xFFFFFFFF);
write32(&infra_ao_mem->emi_idle_bit_en_1, 0xFFFFFFFF);
write32(&infra_ao_mem->emi_idle_bit_en_2, 0xFFFFFFFF);
write32(&infra_ao_mem->emi_idle_bit_en_3, 0xFFFFFFFF);
write32(&infra_ao_mem->emi_m0m1_idle_bit_en_0, 0x01F00000);
write32(&infra_ao_mem->emi_m0m1_idle_bit_en_1, 0xC0040180);
write32(&infra_ao_mem->emi_m0m1_idle_bit_en_2, 0x00000000);
write32(&infra_ao_mem->emi_m0m1_idle_bit_en_3, 0x00000003);
write32(&infra_ao_mem->emi_m2m5_idle_bit_en_0, 0x0C000000);
write32(&infra_ao_mem->emi_m2m5_idle_bit_en_1, 0x00C00000);
write32(&infra_ao_mem->emi_m2m5_idle_bit_en_2, 0x01F08000);
write32(&infra_ao_mem->emi_m2m5_idle_bit_en_3, 0x00000000);
write32(&infra_ao_mem->emi_m3_idle_bit_en_0, 0x20003040);
write32(&infra_ao_mem->emi_m3_idle_bit_en_1, 0x00000000);
write32(&infra_ao_mem->emi_m3_idle_bit_en_2, 0x00001000);
write32(&infra_ao_mem->emi_m3_idle_bit_en_3, 0x00000000);
write32(&infra_ao_mem->emi_m4_idle_bit_en_0, 0x10020F20);
write32(&infra_ao_mem->emi_m4_idle_bit_en_1, 0x00019000);
write32(&infra_ao_mem->emi_m4_idle_bit_en_2, 0x040A0818);
write32(&infra_ao_mem->emi_m4_idle_bit_en_3, 0x00000370);
write32(&infra_ao_mem->emi_m6m7_idle_bit_en_0, 0xC001C080);
write32(&infra_ao_mem->emi_m6m7_idle_bit_en_1, 0x33000E01);
write32(&infra_ao_mem->emi_m6m7_idle_bit_en_2, 0x180067E1);
write32(&infra_ao_mem->emi_m6m7_idle_bit_en_3, 0x000C008C);
write32(&infra_ao_mem->emi_sram_idle_bit_en_0, 0x020C0008);
write32(&infra_ao_mem->emi_sram_idle_bit_en_1, 0x0C00007E);
write32(&infra_ao_mem->emi_sram_idle_bit_en_2, 0x80050006);
write32(&infra_ao_mem->emi_sram_idle_bit_en_3, 0x00030000);
write32(&infra_ao_mem->emi_dcm_cfg0, 0x0000000F);
write32(&infra_ao_mem->emi_dcm_cfg1, 0x00000000);
write32(&infra_ao_mem->emi_dcm_cfg2, 0x001F0044);
write32(&infra_ao_mem->top_ck_anchor_cfg, 0x200000FF);
setbits32(&mt8192_infracfg->mem_dcm_ctrl, BIT(27));
}
static void dramc_dcm_setting2(void)
{
u32 emi_temp_data;
write32(&infra_ao_mem->emi_disph_cfg, 0x00000007);
write32(&infra_ao_mem->emi_disph_cfg, 0x80000007);
emi_temp_data = read32(&infra_ao_mem->emi_disph_cfg);
emi_temp_data = emi_temp_data & 0xf;
setbits32(&emi_reg->chn_hash0, emi_temp_data);
}
void emi_init2(void)
{
u32 tmp;
u32 bc_bak;
struct emi_chn_regs *emi_chn = &ch->emi_chn;
bc_bak = dramc_get_broadcast();
dramc_set_broadcast(DRAMC_BROADCAST_ON);
setbits32(&emi_chn->conc, 0x1);
setbits32(&emi_reg->conm, BIT(10));
setbits32(&emi_mpu->mpu_ctrl, BIT(4));
clrbits32(&emi_chn->rkarb0, 0x1);
tmp = read32(&emi_chn->cona) & 0x1;
setbits32(&emi_chn->rkarb0, tmp);
dramc_dcm_setting();
/* do basic memory read/write for adjusting EMI HW settings */
write32((void *)_dram, read32((void *)_dram));
write32((void *)(_dram + 0x100), read32((void *)(_dram + 0x100)));
write32((void *)(_dram + 0x200), read32((void *)(_dram + 0x200)));
write32((void *)(_dram + 0x300), read32((void *)(_dram + 0x300)));
setbits32(&emi_reg->conn, BIT(22));
setbits32(&emi_chn->testc, BIT(2));
dramc_dcm_setting2();
setbits32(&emi_reg->conn, BIT(21));
setbits32(&emi_chn->testc, BIT(4));
write32(&emi_chn->ebg_con, 0x40);
dramc_set_broadcast(DRAMC_BROADCAST_OFF);
emi_sw_setting();
dramc_set_broadcast(bc_bak);
}
size_t sdram_size(void)
{
size_t dram_size = 0x100000000;
return dram_size;
}
void mt_set_emi(struct dramc_param *dparam)
{
init_dram(&dparam->dramc_datas);
}

972
src/soc/mediatek/mt8192/include/soc/dramc_ac_timing.h
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@ -1,972 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
#define __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__
#include <stdint.h>
#include <sys/types.h>
#include <soc/dramc_common_mt8192.h>
#include <soc/dramc_pi_api.h>
/* Normal Mode and Byte Mode */
#define AC_TIMING_NUMBER (DDRFREQ_MAX * 2)
struct ac_timing {
u8 cbt_mode, read_dbi;
u8 div_mode;
u16 freq_group;
u16 read_lat, write_lat;
u16 dqsinctl, datlat;
u16 tras;
u16 trp;
u16 trpab;
u16 trc;
u16 trfc;
u16 trfcpb;
u16 txp;
u16 trtp;
u16 trcd;
u16 twr;
u16 twtr;
u16 tpbr2pbr;
u16 tpbr2act;
u16 tr2mrw;
u16 tw2mrw;
u16 tmrr2mrw;
u16 tmrw;
u16 tmrd;
u16 tmrwckel;
u16 tpde;
u16 tpdx;
u16 tmrri;
u16 trrd;
u16 trrd_4266;
u16 tfaw;
u16 tfaw_4266;
u16 trtw_odt_off;
u16 trtw_odt_on;
u16 txrefcnt;
u16 tzqcs;
u16 xrtw2w_new_mode;
u16 xrtw2w_old_mode;
u16 xrtw2r_odt_on;
u16 xrtw2r_odt_off;
u16 xrtr2w_odt_on;
u16 xrtr2w_odt_off;
u16 xrtr2r_new_mode;
u16 xrtr2r_old_mode;
u16 tr2mrr;
u16 vrcgdis_prdcnt;
u16 hwset_mr2_op;
u16 hwset_mr13_op;
u16 hwset_vrcg_op;
u16 trcd_derate;
u16 trc_derate;
u16 tras_derate;
u16 trpab_derate;
u16 trp_derate;
u16 trrd_derate;
u16 trtpd;
u16 twtpd;
u16 tmrr2w_odt_off;
u16 tmrr2w_odt_on;
u16 ckeprd;
u16 ckelckcnt;
u16 zqlat2;
u16 tras_05T;
u16 trp_05T;
u16 trpab_05T;
u16 trc_05T;
u16 trfc_05T;
u16 trfcpb_05T;
u16 txp_05T;
u16 trtp_05T;
u16 trcd_05T;
u16 twr_05T;
u16 twtr_05T;
u16 tpbr2pbr_05T;
u16 tpbr2act_05T;
u16 tr2mrw_05T;
u16 tw2mrw_05T;
u16 tmrr2mrw_05T;
u16 tmrw_05T;
u16 tmrd_05T;
u16 tmrwckel_05T;
u16 tpde_05T;
u16 tpdx_05T;
u16 tmrri_05T;
u16 trrd_05T;
u16 trrd_4266_05T;
u16 tfaw_05T;
u16 tfaw_4266_05T;
u16 trtw_odt_off_05T;
u16 trtw_odt_on_05T;
u16 trcd_derate_05T;
u16 trc_derate_05T;
u16 tras_derate_05T;
u16 trpab_derate_05T;
u16 trp_derate_05T;
u16 trrd_derate_05T;
u16 trtpd_05T;
u16 twtpd_05T;
};
/* Normal Mode and Byte Mode for each frequency */
static const struct ac_timing ac_timing_tbl[AC_TIMING_NUMBER] = {
{
.freq_group = DDRFREQ_2133, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
.read_lat = 36, .write_lat = 18, .div_mode = DIV8_MODE,
.tras = 14, .tras_05T = 0,
.trp = 8, .trp_05T = 1,
.trpab = 10, .trpab_05T = 0,
.trc = 23, .trc_05T = 0,
.trfc = 137, .trfc_05T = 1,
.trfcpb = 63, .trfcpb_05T = 0,
.txp = 1, .txp_05T = 0,
.trtp = 2, .trtp_05T = 1,
.trcd = 10, .trcd_05T = 0,
.twr = 15, .twr_05T = 0,
.twtr = 10, .twtr_05T = 1,
.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 17, .tr2mrw_05T = 0,
.tw2mrw = 11, .tw2mrw_05T = 0,
.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
.tmrw = 6, .tmrw_05T = 0,
.tmrd = 8, .tmrd_05T = 0,
.tmrwckel = 9, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 14, .tmrri_05T = 0,
.trrd = 4, .trrd_05T = 1,
.trrd_4266 = 3, .trrd_4266_05T = 0,
.tfaw = 13, .tfaw_05T = 1,
.tfaw_4266 = 8, .tfaw_4266_05T = 0,
.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
.trtw_odt_on = 8, .trtw_odt_on_05T = 0,
.txrefcnt = 154,
.tzqcs = 46,
.xrtw2w_new_mode = 5,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 1,
.xrtw2r_odt_off = 1,
.xrtr2w_odt_on = 7,
.xrtr2w_odt_off = 7,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 7,
.tr2mrr = 4,
.vrcgdis_prdcnt = 54,
.hwset_mr2_op = 63,
.hwset_mr13_op = 216,
.hwset_vrcg_op = 208,
.trcd_derate = 11, .trcd_derate_05T = 0,
.trc_derate = 26, .trc_derate_05T = 0,
.tras_derate = 15, .tras_derate_05T = 0,
.trpab_derate = 11, .trpab_derate_05T = 0,
.trp_derate = 9, .trp_derate_05T = 1,
.trrd_derate = 5, .trrd_derate_05T = 1,
.trtpd = 14, .trtpd_05T = 1,
.twtpd = 18, .twtpd_05T = 0,
.tmrr2w_odt_off = 10,
.tmrr2w_odt_on = 12,
.ckeprd = 3,
.ckelckcnt = 3,
.zqlat2 = 16,
.dqsinctl = 7, .datlat = 18
},
{
.freq_group = DDRFREQ_2133, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
.read_lat = 40, .write_lat = 18, .div_mode = DIV8_MODE,
.tras = 14, .tras_05T = 0,
.trp = 8, .trp_05T = 1,
.trpab = 10, .trpab_05T = 0,
.trc = 23, .trc_05T = 0,
.trfc = 137, .trfc_05T = 1,
.trfcpb = 63, .trfcpb_05T = 0,
.txp = 1, .txp_05T = 0,
.trtp = 2, .trtp_05T = 1,
.trcd = 10, .trcd_05T = 0,
.twr = 16, .twr_05T = 0,
.twtr = 11, .twtr_05T = 1,
.tpbr2pbr = 41, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 18, .tr2mrw_05T = 0,
.tw2mrw = 11, .tw2mrw_05T = 0,
.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
.tmrw = 6, .tmrw_05T = 0,
.tmrd = 8, .tmrd_05T = 0,
.tmrwckel = 9, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 14, .tmrri_05T = 0,
.trrd = 4, .trrd_05T = 1,
.trrd_4266 = 3, .trrd_4266_05T = 0,
.tfaw = 13, .tfaw_05T = 1,
.tfaw_4266 = 8, .tfaw_4266_05T = 0,
.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
.trtw_odt_on = 9, .trtw_odt_on_05T = 0,
.txrefcnt = 154,
.tzqcs = 46,
.xrtw2w_new_mode = 5,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 1,
.xrtw2r_odt_off = 1,
.xrtr2w_odt_on = 8,
.xrtr2w_odt_off = 8,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 7,
.tr2mrr = 4,
.vrcgdis_prdcnt = 54,
.hwset_mr2_op = 63,
.hwset_mr13_op = 216,
.hwset_vrcg_op = 208,
.trcd_derate = 11, .trcd_derate_05T = 0,
.trc_derate = 26, .trc_derate_05T = 0,
.tras_derate = 15, .tras_derate_05T = 0,
.trpab_derate = 11, .trpab_derate_05T = 0,
.trp_derate = 9, .trp_derate_05T = 1,
.trrd_derate = 5, .trrd_derate_05T = 1,
.trtpd = 15, .trtpd_05T = 1,
.twtpd = 19, .twtpd_05T = 0,
.tmrr2w_odt_off = 11,
.tmrr2w_odt_on = 13,
.ckeprd = 3,
.ckelckcnt = 3,
.zqlat2 = 16,
.dqsinctl = 7, .datlat = 18
},
{
.freq_group = DDRFREQ_1600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
.read_lat = 28, .write_lat = 14, .div_mode = DIV8_MODE,
.tras = 8, .tras_05T = 1,
.trp = 6, .trp_05T = 0,
.trpab = 7, .trpab_05T = 0,
.trc = 15, .trc_05T = 0,
.trfc = 100, .trfc_05T = 0,
.trfcpb = 44, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 1, .trtp_05T = 1,
.trcd = 7, .trcd_05T = 1,
.twr = 12, .twr_05T = 1,
.twtr = 7, .twtr_05T = 0,
.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 13, .tr2mrw_05T = 1,
.tw2mrw = 9, .tw2mrw_05T = 0,
.tmrr2mrw = 11, .tmrr2mrw_05T = 1,
.tmrw = 4, .tmrw_05T = 1,
.tmrd = 6, .tmrd_05T = 1,
.tmrwckel = 7, .tmrwckel_05T = 1,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 10, .tmrri_05T = 1,
.trrd = 3, .trrd_05T = 0,
.trrd_4266 = 2, .trrd_4266_05T = 0,
.tfaw = 8, .tfaw_05T = 0,
.tfaw_4266 = 4, .tfaw_4266_05T = 0,
.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
.txrefcnt = 115,
.tzqcs = 34,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 1,
.xrtw2r_odt_off = 1,
.xrtr2w_odt_on = 5,
.xrtr2w_odt_off = 5,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 7,
.tr2mrr = 4,
.vrcgdis_prdcnt = 40,
.hwset_mr2_op = 45,
.hwset_mr13_op = 216,
.hwset_vrcg_op = 208,
.trcd_derate = 8, .trcd_derate_05T = 0,
.trc_derate = 17, .trc_derate_05T = 0,
.tras_derate = 9, .tras_derate_05T = 1,
.trpab_derate = 8, .trpab_derate_05T = 0,
.trp_derate = 6, .trp_derate_05T = 1,
.trrd_derate = 4, .trrd_derate_05T = 0,
.trtpd = 12, .trtpd_05T = 0,
.twtpd = 14, .twtpd_05T = 1,
.tmrr2w_odt_off = 8,
.tmrr2w_odt_on = 10,
.ckeprd = 2,
.ckelckcnt = 2,
.zqlat2 = 12,
.dqsinctl = 5, .datlat = 15
},
{
.freq_group = DDRFREQ_1600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
.read_lat = 32, .write_lat = 14, .div_mode = DIV8_MODE,
.tras = 8, .tras_05T = 1,
.trp = 6, .trp_05T = 0,
.trpab = 7, .trpab_05T = 0,
.trc = 15, .trc_05T = 0,
.trfc = 100, .trfc_05T = 0,
.trfcpb = 44, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 1, .trtp_05T = 1,
.trcd = 7, .trcd_05T = 1,
.twr = 12, .twr_05T = 1,
.twtr = 8, .twtr_05T = 0,
.tpbr2pbr = 29, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 14, .tr2mrw_05T = 1,
.tw2mrw = 9, .tw2mrw_05T = 0,
.tmrr2mrw = 12, .tmrr2mrw_05T = 1,
.tmrw = 4, .tmrw_05T = 1,
.tmrd = 6, .tmrd_05T = 1,
.tmrwckel = 7, .tmrwckel_05T = 1,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 10, .tmrri_05T = 1,
.trrd = 3, .trrd_05T = 0,
.trrd_4266 = 2, .trrd_4266_05T = 0,
.tfaw = 8, .tfaw_05T = 0,
.tfaw_4266 = 4, .tfaw_4266_05T = 0,
.trtw_odt_off = 5, .trtw_odt_off_05T = 0,
.trtw_odt_on = 7, .trtw_odt_on_05T = 0,
.txrefcnt = 115,
.tzqcs = 34,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 1,
.xrtw2r_odt_off = 1,
.xrtr2w_odt_on = 6,
.xrtr2w_odt_off = 6,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 7,
.tr2mrr = 4,
.vrcgdis_prdcnt = 40,
.hwset_mr2_op = 45,
.hwset_mr13_op = 216,
.hwset_vrcg_op = 208,
.trcd_derate = 8, .trcd_derate_05T = 0,
.trc_derate = 17, .trc_derate_05T = 0,
.tras_derate = 9, .tras_derate_05T = 1,
.trpab_derate = 8, .trpab_derate_05T = 0,
.trp_derate = 6, .trp_derate_05T = 1,
.trrd_derate = 4, .trrd_derate_05T = 0,
.trtpd = 13, .trtpd_05T = 0,
.twtpd = 15, .twtpd_05T = 1,
.tmrr2w_odt_off = 9,
.tmrr2w_odt_on = 11,
.ckeprd = 2,
.ckelckcnt = 2,
.zqlat2 = 12,
.dqsinctl = 5, .datlat = 15
},
{
.freq_group = DDRFREQ_1200, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
.read_lat = 24, .write_lat = 12, .div_mode = DIV8_MODE,
.tras = 4, .tras_05T = 1,
.trp = 4, .trp_05T = 0,
.trpab = 5, .trpab_05T = 0,
.trc = 9, .trc_05T = 1,
.trfc = 72, .trfc_05T = 1,
.trfcpb = 30, .trfcpb_05T = 1,
.txp = 0, .txp_05T = 1,
.trtp = 1, .trtp_05T = 0,
.trcd = 5, .trcd_05T = 1,
.twr = 9, .twr_05T = 1,
.twtr = 6, .twtr_05T = 1,
.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 12, .tr2mrw_05T = 0,
.tw2mrw = 8, .tw2mrw_05T = 0,
.tmrr2mrw = 10, .tmrr2mrw_05T = 0,
.tmrw = 4, .tmrw_05T = 0,
.tmrd = 5, .tmrd_05T = 0,
.tmrwckel = 6, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 8, .tmrri_05T = 0,
.trrd = 2, .trrd_05T = 1,
.trrd_4266 = 1, .trrd_4266_05T = 1,
.tfaw = 4, .tfaw_05T = 1,
.tfaw_4266 = 1, .tfaw_4266_05T = 1,
.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
.txrefcnt = 87,
.tzqcs = 26,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 2,
.xrtw2r_odt_off = 2,
.xrtr2w_odt_on = 5,
.xrtr2w_odt_off = 5,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 31,
.hwset_mr2_op = 36,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 6, .trcd_derate_05T = 0,
.trc_derate = 10, .trc_derate_05T = 1,
.tras_derate = 5, .tras_derate_05T = 0,
.trpab_derate = 5, .trpab_derate_05T = 1,
.trp_derate = 4, .trp_derate_05T = 1,
.trrd_derate = 3, .trrd_derate_05T = 0,
.trtpd = 10, .trtpd_05T = 1,
.twtpd = 12, .twtpd_05T = 0,
.tmrr2w_odt_off = 6,
.tmrr2w_odt_on = 8,
.ckeprd = 2,
.ckelckcnt = 2,
.zqlat2 = 10,
.dqsinctl = 4, .datlat = 13
},
{
.freq_group = DDRFREQ_1200, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
.read_lat = 26, .write_lat = 12, .div_mode = DIV8_MODE,
.tras = 4, .tras_05T = 1,
.trp = 4, .trp_05T = 0,
.trpab = 5, .trpab_05T = 0,
.trc = 9, .trc_05T = 1,
.trfc = 72, .trfc_05T = 1,
.trfcpb = 30, .trfcpb_05T = 1,
.txp = 0, .txp_05T = 1,
.trtp = 1, .trtp_05T = 0,
.trcd = 5, .trcd_05T = 1,
.twr = 10, .twr_05T = 0,
.twtr = 6, .twtr_05T = 0,
.tpbr2pbr = 20, .tpbr2pbr_05T = 1,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 12, .tr2mrw_05T = 1,
.tw2mrw = 8, .tw2mrw_05T = 0,
.tmrr2mrw = 10, .tmrr2mrw_05T = 1,
.tmrw = 4, .tmrw_05T = 0,
.tmrd = 5, .tmrd_05T = 0,
.tmrwckel = 6, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 8, .tmrri_05T = 0,
.trrd = 2, .trrd_05T = 1,
.trrd_4266 = 1, .trrd_4266_05T = 1,
.tfaw = 4, .tfaw_05T = 1,
.tfaw_4266 = 1, .tfaw_4266_05T = 1,
.trtw_odt_off = 4, .trtw_odt_off_05T = 0,
.trtw_odt_on = 6, .trtw_odt_on_05T = 0,
.txrefcnt = 87,
.tzqcs = 26,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 1,
.xrtw2r_odt_off = 1,
.xrtr2w_odt_on = 5,
.xrtr2w_odt_off = 5,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 31,
.hwset_mr2_op = 36,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 6, .trcd_derate_05T = 0,
.trc_derate = 10, .trc_derate_05T = 1,
.tras_derate = 5, .tras_derate_05T = 0,
.trpab_derate = 5, .trpab_derate_05T = 1,
.trp_derate = 4, .trp_derate_05T = 1,
.trrd_derate = 3, .trrd_derate_05T = 0,
.trtpd = 11, .trtpd_05T = 0,
.twtpd = 13, .twtpd_05T = 0,
.tmrr2w_odt_off = 7,
.tmrr2w_odt_on = 9,
.ckeprd = 2,
.ckelckcnt = 2,
.zqlat2 = 10,
.dqsinctl = 4, .datlat = 13
},
{
.freq_group = DDRFREQ_933, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
.read_lat = 20, .write_lat = 10, .div_mode = DIV8_MODE,
.tras = 1, .tras_05T = 1,
.trp = 3, .trp_05T = 0,
.trpab = 3, .trpab_05T = 1,
.trc = 5, .trc_05T = 0,
.trfc = 53, .trfc_05T = 1,
.trfcpb = 21, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 0, .trtp_05T = 1,
.trcd = 4, .trcd_05T = 1,
.twr = 8, .twr_05T = 1,
.twtr = 5, .twtr_05T = 1,
.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 10, .tr2mrw_05T = 0,
.tw2mrw = 7, .tw2mrw_05T = 0,
.tmrr2mrw = 9, .tmrr2mrw_05T = 0,
.tmrw = 3, .tmrw_05T = 0,
.tmrd = 4, .tmrd_05T = 0,
.tmrwckel = 5, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 6, .tmrri_05T = 0,
.trrd = 1, .trrd_05T = 1,
.trrd_4266 = 1, .trrd_4266_05T = 0,
.tfaw = 1, .tfaw_05T = 1,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
.txrefcnt = 68,
.tzqcs = 19,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 2,
.xrtw2r_odt_off = 2,
.xrtr2w_odt_on = 3,
.xrtr2w_odt_off = 3,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 24,
.hwset_mr2_op = 27,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 5, .trcd_derate_05T = 0,
.trc_derate = 6, .trc_derate_05T = 1,
.tras_derate = 2, .tras_derate_05T = 0,
.trpab_derate = 4, .trpab_derate_05T = 0,
.trp_derate = 3, .trp_derate_05T = 1,
.trrd_derate = 2, .trrd_derate_05T = 0,
.trtpd = 9, .trtpd_05T = 1,
.twtpd = 10, .twtpd_05T = 1,
.tmrr2w_odt_off = 5,
.tmrr2w_odt_on = 7,
.ckeprd = 1,
.ckelckcnt = 2,
.zqlat2 = 7,
.dqsinctl = 3, .datlat = 13
},
{
.freq_group = DDRFREQ_933, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
.read_lat = 22, .write_lat = 10, .div_mode = DIV8_MODE,
.tras = 1, .tras_05T = 1,
.trp = 3, .trp_05T = 0,
.trpab = 3, .trpab_05T = 1,
.trc = 5, .trc_05T = 0,
.trfc = 53, .trfc_05T = 1,
.trfcpb = 21, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 0, .trtp_05T = 1,
.trcd = 4, .trcd_05T = 1,
.twr = 8, .twr_05T = 0,
.twtr = 5, .twtr_05T = 0,
.tpbr2pbr = 14, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 10, .tr2mrw_05T = 1,
.tw2mrw = 7, .tw2mrw_05T = 0,
.tmrr2mrw = 9, .tmrr2mrw_05T = 1,
.tmrw = 3, .tmrw_05T = 0,
.tmrd = 4, .tmrd_05T = 0,
.tmrwckel = 5, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 6, .tmrri_05T = 0,
.trrd = 1, .trrd_05T = 1,
.trrd_4266 = 1, .trrd_4266_05T = 0,
.tfaw = 1, .tfaw_05T = 1,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 3, .trtw_odt_off_05T = 0,
.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
.txrefcnt = 68,
.tzqcs = 19,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 2,
.xrtw2r_odt_off = 1,
.xrtr2w_odt_on = 4,
.xrtr2w_odt_off = 4,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 24,
.hwset_mr2_op = 27,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 5, .trcd_derate_05T = 0,
.trc_derate = 6, .trc_derate_05T = 1,
.tras_derate = 2, .tras_derate_05T = 0,
.trpab_derate = 4, .trpab_derate_05T = 0,
.trp_derate = 3, .trp_derate_05T = 1,
.trrd_derate = 2, .trrd_derate_05T = 0,
.trtpd = 10, .trtpd_05T = 0,
.twtpd = 11, .twtpd_05T = 0,
.tmrr2w_odt_off = 6,
.tmrr2w_odt_on = 8,
.ckeprd = 1,
.ckelckcnt = 2,
.zqlat2 = 7,
.dqsinctl = 3, .datlat = 13
},
{
.freq_group = DDRFREQ_800, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
.read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE,
.tras = 0, .tras_05T = 0,
.trp = 2, .trp_05T = 1,
.trpab = 3, .trpab_05T = 0,
.trc = 3, .trc_05T = 0,
.trfc = 44, .trfc_05T = 0,
.trfcpb = 16, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 0, .trtp_05T = 1,
.trcd = 4, .trcd_05T = 0,
.twr = 7, .twr_05T = 1,
.twtr = 4, .twtr_05T = 1,
.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 8, .tr2mrw_05T = 1,
.tw2mrw = 6, .tw2mrw_05T = 1,
.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
.tmrw = 3, .tmrw_05T = 0,
.tmrd = 3, .tmrd_05T = 1,
.tmrwckel = 4, .tmrwckel_05T = 1,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 5, .tmrri_05T = 1,
.trrd = 1, .trrd_05T = 0,
.trrd_4266 = 0, .trrd_4266_05T = 1,
.tfaw = 0, .tfaw_05T = 0,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
.txrefcnt = 58,
.tzqcs = 16,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 3,
.xrtw2r_odt_off = 3,
.xrtr2w_odt_on = 3,
.xrtr2w_odt_off = 3,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 20,
.hwset_mr2_op = 18,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 4, .trcd_derate_05T = 0,
.trc_derate = 4, .trc_derate_05T = 0,
.tras_derate = 0, .tras_derate_05T = 1,
.trpab_derate = 3, .trpab_derate_05T = 1,
.trp_derate = 2, .trp_derate_05T = 1,
.trrd_derate = 1, .trrd_derate_05T = 1,
.trtpd = 7, .trtpd_05T = 1,
.twtpd = 9, .twtpd_05T = 1,
.tmrr2w_odt_off = 3,
.tmrr2w_odt_on = 5,
.ckeprd = 1,
.ckelckcnt = 2,
.zqlat2 = 6,
.dqsinctl = 2, .datlat = 10
},
{
.freq_group = DDRFREQ_800, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
.read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE,
.tras = 0, .tras_05T = 0,
.trp = 2, .trp_05T = 1,
.trpab = 3, .trpab_05T = 0,
.trc = 3, .trc_05T = 0,
.trfc = 44, .trfc_05T = 0,
.trfcpb = 16, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 0, .trtp_05T = 1,
.trcd = 4, .trcd_05T = 0,
.twr = 7, .twr_05T = 0,
.twtr = 4, .twtr_05T = 0,
.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 9, .tr2mrw_05T = 0,
.tw2mrw = 6, .tw2mrw_05T = 1,
.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
.tmrw = 3, .tmrw_05T = 0,
.tmrd = 3, .tmrd_05T = 1,
.tmrwckel = 4, .tmrwckel_05T = 1,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 5, .tmrri_05T = 1,
.trrd = 1, .trrd_05T = 0,
.trrd_4266 = 0, .trrd_4266_05T = 1,
.tfaw = 0, .tfaw_05T = 0,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
.txrefcnt = 58,
.tzqcs = 16,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 3,
.xrtw2r_odt_off = 2,
.xrtr2w_odt_on = 3,
.xrtr2w_odt_off = 3,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 20,
.hwset_mr2_op = 18,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 4, .trcd_derate_05T = 0,
.trc_derate = 4, .trc_derate_05T = 0,
.tras_derate = 0, .tras_derate_05T = 1,
.trpab_derate = 3, .trpab_derate_05T = 1,
.trp_derate = 2, .trp_derate_05T = 1,
.trrd_derate = 1, .trrd_derate_05T = 1,
.trtpd = 8, .trtpd_05T = 0,
.twtpd = 9, .twtpd_05T = 1,
.tmrr2w_odt_off = 4,
.tmrr2w_odt_on = 6,
.ckeprd = 1,
.ckelckcnt = 2,
.zqlat2 = 6,
.dqsinctl = 2, .datlat = 10
},
{
.freq_group = DDRFREQ_600, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
.read_lat = 14, .write_lat = 8, .div_mode = DIV8_MODE,
.tras = 0, .tras_05T = 0,
.trp = 1, .trp_05T = 1,
.trpab = 2, .trpab_05T = 0,
.trc = 0, .trc_05T = 1,
.trfc = 30, .trfc_05T = 1,
.trfcpb = 9, .trfcpb_05T = 1,
.txp = 0, .txp_05T = 0,
.trtp = 0, .trtp_05T = 1,
.trcd = 3, .trcd_05T = 0,
.twr = 6, .twr_05T = 1,
.twtr = 4, .twtr_05T = 1,
.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 8, .tr2mrw_05T = 1,
.tw2mrw = 6, .tw2mrw_05T = 1,
.tmrr2mrw = 7, .tmrr2mrw_05T = 0,
.tmrw = 3, .tmrw_05T = 0,
.tmrd = 3, .tmrd_05T = 0,
.tmrwckel = 4, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 4, .tmrri_05T = 0,
.trrd = 1, .trrd_05T = 0,
.trrd_4266 = 0, .trrd_4266_05T = 1,
.tfaw = 0, .tfaw_05T = 0,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 1, .trtw_odt_off_05T = 0,
.trtw_odt_on = 4, .trtw_odt_on_05T = 0,
.txrefcnt = 44,
.tzqcs = 12,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 3,
.xrtw2r_odt_off = 3,
.xrtr2w_odt_on = 3,
.xrtr2w_odt_off = 3,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 16,
.hwset_mr2_op = 18,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 3, .trcd_derate_05T = 0,
.trc_derate = 1, .trc_derate_05T = 0,
.tras_derate = 0, .tras_derate_05T = 0,
.trpab_derate = 2, .trpab_derate_05T = 0,
.trp_derate = 1, .trp_derate_05T = 1,
.trrd_derate = 1, .trrd_derate_05T = 0,
.trtpd = 7, .trtpd_05T = 1,
.twtpd = 8, .twtpd_05T = 1,
.tmrr2w_odt_off = 3,
.tmrr2w_odt_on = 5,
.ckeprd = 1,
.ckelckcnt = 2,
.zqlat2 = 5,
.dqsinctl = 2, .datlat = 9
},
{
.freq_group = DDRFREQ_600, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
.read_lat = 16, .write_lat = 8, .div_mode = DIV8_MODE,
.tras = 0, .tras_05T = 0,
.trp = 1, .trp_05T = 1,
.trpab = 2, .trpab_05T = 0,
.trc = 0, .trc_05T = 1,
.trfc = 30, .trfc_05T = 1,
.trfcpb = 9, .trfcpb_05T = 1,
.txp = 0, .txp_05T = 0,
.trtp = 0, .trtp_05T = 1,
.trcd = 3, .trcd_05T = 0,
.twr = 6, .twr_05T = 0,
.twtr = 4, .twtr_05T = 1,
.tpbr2pbr = 7, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 9, .tr2mrw_05T = 0,
.tw2mrw = 6, .tw2mrw_05T = 1,
.tmrr2mrw = 7, .tmrr2mrw_05T = 1,
.tmrw = 3, .tmrw_05T = 0,
.tmrd = 3, .tmrd_05T = 0,
.tmrwckel = 4, .tmrwckel_05T = 0,
.tpde = 1, .tpde_05T = 1,
.tpdx = 1, .tpdx_05T = 0,
.tmrri = 4, .tmrri_05T = 0,
.trrd = 1, .trrd_05T = 0,
.trrd_4266 = 0, .trrd_4266_05T = 1,
.tfaw = 0, .tfaw_05T = 0,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 2, .trtw_odt_off_05T = 0,
.trtw_odt_on = 5, .trtw_odt_on_05T = 0,
.txrefcnt = 44,
.tzqcs = 12,
.xrtw2w_new_mode = 4,
.xrtw2w_old_mode = 6,
.xrtw2r_odt_on = 3,
.xrtw2r_odt_off = 2,
.xrtr2w_odt_on = 3,
.xrtr2w_odt_off = 3,
.xrtr2r_new_mode = 3,
.xrtr2r_old_mode = 6,
.tr2mrr = 4,
.vrcgdis_prdcnt = 16,
.hwset_mr2_op = 18,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 3, .trcd_derate_05T = 0,
.trc_derate = 1, .trc_derate_05T = 0,
.tras_derate = 0, .tras_derate_05T = 0,
.trpab_derate = 2, .trpab_derate_05T = 0,
.trp_derate = 1, .trp_derate_05T = 1,
.trrd_derate = 1, .trrd_derate_05T = 0,
.trtpd = 8, .trtpd_05T = 0,
.twtpd = 9, .twtpd_05T = 0,
.tmrr2w_odt_off = 4,
.tmrr2w_odt_on = 6,
.ckeprd = 1,
.ckelckcnt = 2,
.zqlat2 = 5,
.dqsinctl = 2, .datlat = 9
},
{
.freq_group = DDRFREQ_400, .cbt_mode = CBT_NORMAL_MODE, .read_dbi = 0,
.read_lat = 14, .write_lat = 8, .div_mode = DIV4_MODE,
.tras = 1, .tras_05T = 0,
.trp = 2, .trp_05T = 0,
.trpab = 3, .trpab_05T = 0,
.trc = 3, .trc_05T = 0,
.trfc = 44, .trfc_05T = 0,
.trfcpb = 16, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 3, .trtp_05T = 0,
.trcd = 4, .trcd_05T = 0,
.twr = 12, .twr_05T = 0,
.twtr = 10, .twtr_05T = 0,
.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 16, .tr2mrw_05T = 0,
.tw2mrw = 13, .tw2mrw_05T = 0,
.tmrr2mrw = 14, .tmrr2mrw_05T = 0,
.tmrw = 6, .tmrw_05T = 0,
.tmrd = 6, .tmrd_05T = 0,
.tmrwckel = 8, .tmrwckel_05T = 0,
.tpde = 3, .tpde_05T = 0,
.tpdx = 3, .tpdx_05T = 0,
.tmrri = 7, .tmrri_05T = 0,
.trrd = 1, .trrd_05T = 0,
.trrd_4266 = 1, .trrd_4266_05T = 0,
.tfaw = 0, .tfaw_05T = 0,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 6, .trtw_odt_off_05T = 0,
.trtw_odt_on = 11, .trtw_odt_on_05T = 0,
.txrefcnt = 58,
.tzqcs = 16,
.xrtw2w_new_mode = 9,
.xrtw2w_old_mode = 10,
.xrtw2r_odt_on = 7,
.xrtw2r_odt_off = 5,
.xrtr2w_odt_on = 9,
.xrtr2w_odt_off = 9,
.xrtr2r_new_mode = 6,
.xrtr2r_old_mode = 8,
.tr2mrr = 8,
.vrcgdis_prdcnt = 20,
.hwset_mr2_op = 18,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 4, .trcd_derate_05T = 0,
.trc_derate = 4, .trc_derate_05T = 0,
.tras_derate = 1, .tras_derate_05T = 0,
.trpab_derate = 3, .trpab_derate_05T = 0,
.trp_derate = 2, .trp_derate_05T = 0,
.trrd_derate = 2, .trrd_derate_05T = 0,
.trtpd = 15, .trtpd_05T = 0,
.twtpd = 15, .twtpd_05T = 0,
.tmrr2w_odt_off = 10,
.tmrr2w_odt_on = 12,
.ckeprd = 2,
.ckelckcnt = 3,
.zqlat2 = 6,
.dqsinctl = 5, .datlat = 15
},
{
.freq_group = DDRFREQ_400, .cbt_mode = CBT_BYTE_MODE1, .read_dbi = 0,
.read_lat = 16, .write_lat = 8, .div_mode = DIV4_MODE,
.tras = 1, .tras_05T = 0,
.trp = 2, .trp_05T = 0,
.trpab = 3, .trpab_05T = 0,
.trc = 3, .trc_05T = 0,
.trfc = 44, .trfc_05T = 0,
.trfcpb = 16, .trfcpb_05T = 0,
.txp = 0, .txp_05T = 0,
.trtp = 3, .trtp_05T = 0,
.trcd = 4, .trcd_05T = 0,
.twr = 12, .twr_05T = 0,
.twtr = 10, .twtr_05T = 0,
.tpbr2pbr = 11, .tpbr2pbr_05T = 0,
.tpbr2act = 0, .tpbr2act_05T = 0,
.tr2mrw = 17, .tr2mrw_05T = 0,
.tw2mrw = 13, .tw2mrw_05T = 0,
.tmrr2mrw = 15, .tmrr2mrw_05T = 0,
.tmrw = 6, .tmrw_05T = 0,
.tmrd = 6, .tmrd_05T = 0,
.tmrwckel = 8, .tmrwckel_05T = 0,
.tpde = 3, .tpde_05T = 0,
.tpdx = 3, .tpdx_05T = 0,
.tmrri = 7, .tmrri_05T = 0,
.trrd = 1, .trrd_05T = 0,
.trrd_4266 = 1, .trrd_4266_05T = 0,
.tfaw = 0, .tfaw_05T = 0,
.tfaw_4266 = 0, .tfaw_4266_05T = 0,
.trtw_odt_off = 7, .trtw_odt_off_05T = 0,
.trtw_odt_on = 12, .trtw_odt_on_05T = 0,
.txrefcnt = 58,
.tzqcs = 16,
.xrtw2w_new_mode = 9,
.xrtw2w_old_mode = 10,
.xrtw2r_odt_on = 6,
.xrtw2r_odt_off = 4,
.xrtr2w_odt_on = 10,
.xrtr2w_odt_off = 10,
.xrtr2r_new_mode = 6,
.xrtr2r_old_mode = 9,
.tr2mrr = 8,
.vrcgdis_prdcnt = 20,
.hwset_mr2_op = 18,
.hwset_mr13_op = 24,
.hwset_vrcg_op = 16,
.trcd_derate = 4, .trcd_derate_05T = 0,
.trc_derate = 4, .trc_derate_05T = 0,
.tras_derate = 1, .tras_derate_05T = 0,
.trpab_derate = 3, .trpab_derate_05T = 0,
.trp_derate = 2, .trp_derate_05T = 0,
.trrd_derate = 2, .trrd_derate_05T = 0,
.trtpd = 16, .trtpd_05T = 0,
.twtpd = 15, .twtpd_05T = 0,
.tmrr2w_odt_off = 11,
.tmrr2w_odt_on = 13,
.ckeprd = 2,
.ckelckcnt = 3,
.zqlat2 = 6,
.dqsinctl = 5, .datlat = 15
},
};
#endif /* __SOC_MEDIATEK_MT8192_DRAMC_AC_TIMING_H__ */

63
src/soc/mediatek/mt8192/include/soc/dramc_common_mt8192.h
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@ -1,63 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__
#define __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__
enum {
FSP_0 = 0,
FSP_1,
FSP_MAX,
};
typedef enum {
DRAM_DFS_SHU0 = 0,
DRAM_DFS_SHU1,
DRAM_DFS_SHU2,
DRAM_DFS_SHU3,
DRAM_DFS_SHU4,
DRAM_DFS_SHU5,
DRAM_DFS_SHU6,
DRAM_DFS_SHU_MAX
} dram_dfs_shu;
typedef enum {
ODT_OFF = 0,
ODT_ON,
ODT_MAX
} dram_odt_state;
typedef enum {
DBI_OFF = 0,
DBI_ON
} dbi_mode;
enum {
CKE_FIXOFF = 0,
CKE_FIXON,
CKE_DYNAMIC
};
enum {
CA_NUM_LP4 = 6,
DQ_DATA_WIDTH = 16,
DQS_BIT_NUMBER = 8,
DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER),
};
#define BYTE_NUM DQS_NUMBER
/* DONOT change the sequence of pinmux */
typedef enum {
PINMUX_DSC = 0,
PINMUX_LPBK,
PINMUX_EMCP,
PINMUX_MAX
} dram_pinmux_type;
enum {
CBT_R0_R1_NORMAL = 0,
CBT_R0_R1_BYTE,
CBT_R0_NORMAL_R1_BYTE,
CBT_R0_BYTE_R1_NORMAL
};
#endif /* __SOC_MEDIATEK_MT8192_DRAMC_COMMON_MT8192_H__ */

352
src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__
#define __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__
#include <console/console.h>
#include <delay.h>
#include <device/mmio.h>
#include <stdint.h>
#include <types.h>
#include <soc/addressmap.h>
#include <soc/dramc_common_mt8192.h>
#include <soc/dramc_register_bits_def.h>
#include <soc/emi.h>
#define dramc_err(_x_...) printk(BIOS_ERR, _x_)
#define dramc_info(_x_...) printk(BIOS_INFO, _x_)
#if CONFIG(DEBUG_DRAM)
#define dramc_dbg(_x_...) printk(BIOS_INFO, _x_)
#else
#define dramc_dbg(_x_...)
#endif
#define DRAMC_BROADCAST_ON 0x7f
#define DRAMC_BROADCAST_OFF 0x0
#define TX_DQ_UI_TO_PI_TAP 64
#define TX_PHASE_DQ_UI_TO_PI_TAP 32
#define LP4_TX_VREF_DATA_NUM 50
#define LP4_TX_VREF_PASS_CONDITION 0
#define TX_PASS_WIN_CRITERIA 7
#define LP4_TX_VREF_BOUNDARY_NOT_READY 0xff
#define REG_SHU_OFFSET_WIDTH 0x700
#define SHU_OFFSET (REG_SHU_OFFSET_WIDTH / 4)
#define DQS_LEVEL_UNKNOWN 0xff
typedef enum {
DDRFREQ_400,
DDRFREQ_600,
DDRFREQ_800,
DDRFREQ_933,
DDRFREQ_1200,
DDRFREQ_1600,
DDRFREQ_2133,
DDRFREQ_MAX,
} dram_freq_grp;
typedef enum {
CALI_SEQ0 = 0,
CALI_SEQ1,
CALI_SEQ2,
CALI_SEQ3,
CALI_SEQ4,
CALI_SEQ5,
CALI_SEQ6,
CALI_SEQ_MAX
} dram_cali_seq;
typedef enum {
DIV8_MODE = 0,
DIV4_MODE,
UNKNOWN_MODE,
} dram_div_mode;
typedef enum {
VREF_CALI_OFF = 0,
VREF_CALI_ON,
} vref_cali_mode;
typedef enum {
DRVP = 0,
DRVN,
ODTP,
ODTN,
IMP_DRV_MAX
} imp_drv_type;
typedef enum {
RX_WIN_RD_DQC = 0,
RX_WIN_TEST_ENG,
} rx_cali_type;
typedef enum TX_CAL_TYPE {
TX_DQ_DQS_MOVE_DQ_ONLY,
TX_DQ_DQS_MOVE_DQM_ONLY,
TX_DQ_DQS_MOVE_DQ_DQM,
} tx_cali_type;
typedef enum {
DCM_OFF = 0,
DCM_ON,
} dcm_state;
typedef enum {
CBT_LOW_FREQ = 0,
CBT_HIGH_FREQ,
CBT_UNKNOWN_FREQ = 0xff,
} cbt_freq;
typedef enum {
IN_CBT,
OUT_CBT,
} cbt_state;
enum {
PHYPLL_MODE = 0,
CLRPLL_MODE,
};
enum {
DUTYSCAN_K_DQ,
DUTYSCAN_K_DQM,
};
typedef enum {
O1_OFF,
O1_ON,
} o1_state;
typedef enum {
SINGLE_RANK_DDR = 1,
DUAL_RANK_DDR
} ddr_rank_num;
enum {
DQS_8PH_DEGREE_0 = 0,
DQS_8PH_DEGREE_180,
DQS_8PH_DEGREE_45,
DQS_8PH_DEGREE_MAX,
};
struct dram_impedance {
u32 result[ODT_MAX][IMP_DRV_MAX];
};
struct mr_values {
u8 mr01[FSP_MAX];
u8 mr02[FSP_MAX];
u8 mr03[FSP_MAX];
u8 mr04[RANK_MAX];
u8 mr11[FSP_MAX];
u8 mr12[CHANNEL_MAX][RANK_MAX][FSP_MAX];
u8 mr13[RANK_MAX];
u8 mr14[CHANNEL_MAX][RANK_MAX][FSP_MAX];
u8 mr18[CHANNEL_MAX][RANK_MAX];
u8 mr19[CHANNEL_MAX][RANK_MAX];
u8 mr20[FSP_MAX];
u8 mr21[FSP_MAX];
u8 mr22[FSP_MAX];
u8 mr23[CHANNEL_MAX][RANK_MAX];
u8 mr26[RANK_MAX];
u8 mr30[RANK_MAX];
u8 mr51[FSP_MAX];
};
struct ddr_cali {
u8 chn;
u8 rank;
/*
* frequency set point:
* 0 means lower,un-terminated freq;
* 1 means higher,terminated freq
*/
u8 fsp;
u8 density;
u8 *pll_mode;
u32 frequency;
u32 vcore_voltage;
dram_dfs_shu shu;
ddr_rank_num support_ranks;
dbi_mode w_dbi[FSP_MAX];
vref_cali_mode vref_cali;
dram_odt_state odt_onoff;
dram_freq_grp freq_group;
dram_div_mode div_mode;
dram_pinmux_type pinmux_type;
dram_cbt_mode cbt_mode[RANK_MAX];
struct dram_impedance impedance;
struct mr_values *mr_value;
const struct emi_mdl *emi_config;
const struct sdram_params *params;
};
struct reg_bak {
u32 *addr;
u32 value;
};
typedef struct _ana_top_config {
u8 dll_async_en;
u8 all_slave_en;
u8 rank_mode;
u8 dll_idle_mode;
u8 aphy_comb_en;
u8 tx_odt_dis;
u8 new_8x_mode;
} ana_top_config;
typedef struct ana_dvfs_core_config {
u8 ckr;
u8 dq_p2s_ratio;
u8 ca_p2s_ratio;
u8 dq_ca_open;
u8 dq_semi_open;
u8 ca_semi_open;
u8 ca_full_rate;
u8 dq_ckdiv4_en;
u8 ca_ckdiv4_en;
u8 ca_prediv_en;
u8 ph8_dly;
u8 semi_open_ca_pick_mck_ratio;
u8 dq_aamck_div;
u8 ca_admck_div;
u8 dq_track_ca_en;
u32 pll_freq;
} ana_dvfs_core;
typedef struct lp4_dram_config {
u8 ex_row_en[RANK_MAX];
u8 mr_wl;
u8 dbi_wr;
u8 dbi_rd;
u8 lp4y_en;
u8 work_fsp;
} dram_config;
typedef struct _dvfs_group_config {
u32 data_rate;
u8 dqsien_mode;
u8 dq_p2s_ratio;
u8 ckr;
} dvfs_group_config;
struct gating_config {
u8 gat_track_en;
u8 rx_gating_mode;
u8 rx_gating_track_mode;
u8 valid_lat_value;
};
typedef struct _dramc_subsys_config {
dram_freq_grp freq_group;
ana_top_config *a_cfg;
ana_dvfs_core *dvfs_core;
dram_config *lp4_init;
dvfs_group_config *dfs_gp;
struct gating_config *gat_c;
} dramc_subsys_config;
typedef struct _reg_transfer {
u32 *addr;
u8 offset;
} reg_transfer;
void emi_init2(void);
u32 get_column_num(void);
u32 get_row_width_from_emi(u32 rank);
u8 dramc_mode_reg_read(u8 chn, u8 mr_idx);
u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx);
void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali,
u8 chn, u8 rank, u8 mr_idx, u8 value);
void after_calib(const struct ddr_cali *cali);
void init_dram(const struct dramc_data *dparam);
void global_option_init(struct ddr_cali *cali);
u32 dramc_get_broadcast(void);
void dramc_set_broadcast(u32 onoff);
void dramc_sw_impedance_cal(dram_odt_state odt, struct dram_impedance *imp);
void dramc_sw_impedance_save_register(const struct ddr_cali *cali);
void dfs_init_for_calibration(const struct ddr_cali *cali);
void dramc_auto_refresh_switch(u8 chn, bool flag);
void dramc_runtime_config(const struct ddr_cali *cali);
void emi_mdl_init(const struct emi_mdl *emi_con);
void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option);
void enable_phy_dcm_shuffle(dcm_state enable, u8 shuffle_save);
void enable_phy_dcm_non_shuffle(dcm_state enable);
void dramc_8_phase_cal(const struct ddr_cali *cali);
void dramc_duty_calibration(const struct sdram_params *params);
void dramc_write_leveling(const struct ddr_cali *cali,
u8 dqs_final_delay[RANK_MAX][DQS_NUMBER]);
void dramc_rx_dqs_gating_cal(const struct ddr_cali *cali, u8 *txdly_min, u8 *txdly_max);
void dramc_rx_dqs_gating_post_process(const struct ddr_cali *cali,
u8 txdly_min, u8 txdly_max);
void dramc_rx_datlat_cal(const struct ddr_cali *cali);
void dramc_dual_rank_rx_datlat_cal(const struct ddr_cali *cali);
void dramc_cmd_bus_training(const struct ddr_cali *cali);
void dramc_rx_window_perbit_cal(const struct ddr_cali *cali, rx_cali_type type);
void dramc_tx_window_perbit_cal(const struct ddr_cali *cali, tx_cali_type cal_type,
const u8 dqs_final_delay[RANK_MAX][DQS_NUMBER], bool vref_scan_enable);
void dramc_tx_oe_calibration(const struct ddr_cali *cali);
dram_freq_grp get_freq_group(const struct ddr_cali *cali);
dram_odt_state get_odt_state(const struct ddr_cali *cali);
u8 get_fsp(const struct ddr_cali *cali);
dram_dfs_shu get_shu(const struct ddr_cali *cali);
dram_freq_grp get_highest_freq_group(void);
dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali);
u32 get_frequency(const struct ddr_cali *cali);
vref_cali_mode get_vref_cali(const struct ddr_cali *cali);
dram_div_mode get_div_mode(const struct ddr_cali *cali);
dbi_mode get_write_dbi(const struct ddr_cali *cali);
dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_seq);
dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu);
dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali);
u32 get_frequency_by_shu(dram_dfs_shu shu);
u32 get_vcore_value(const struct ddr_cali *cali);
void set_cali_datas(struct ddr_cali *cali,
const struct dramc_data *dparam, dram_cali_seq k_seq);
u8 get_mck2ui_div_shift(const struct ddr_cali *cali);
void tx_picg_setting(const struct ddr_cali *cali);
void xrtrtr_shu_setting(const struct ddr_cali *cali);
void cbt_switch_freq(const struct ddr_cali *cali, cbt_freq freq);
void enable_dfs_hw_mode_clk(void);
void dramc_dfs_direct_jump_rg_mode(const struct ddr_cali *cali, u8 shu_level);
void dramc_dfs_direct_jump_sram_shu_rg_mode(const struct ddr_cali *cali,
dram_dfs_shu shu_level);
void dramc_save_result_to_shuffle(dram_dfs_shu src, dram_dfs_shu dst);
void dramc_load_shuffle_to_dramc(dram_dfs_shu src, dram_dfs_shu dst);
void dvfs_settings(const struct ddr_cali *cali);
void dramc_dqs_precalculation_preset(const struct ddr_cali *cali);
void freq_jump_ratio_calculation(const struct ddr_cali *cali);
void dramc_hmr4_presetting(const struct ddr_cali *cali);
void dramc_enable_perbank_refresh(bool en);
void dramc_modified_refresh_mode(void);
void dramc_cke_debounce(const struct ddr_cali *cali);
void dramc_hw_dqsosc(const struct ddr_cali *cali, u8 chn);
void xrtwtw_shu_setting(const struct ddr_cali *cali);
void enable_write_DBI_after_calibration(const struct ddr_cali *cali);
void dramc_set_mr13_vrcg_to_normal(const struct ddr_cali *cali);
void ana_init(const struct ddr_cali *cali, dramc_subsys_config *subsys);
void dig_static_setting(const struct ddr_cali *cali, dramc_subsys_config *subsys);
void dig_config_shuf(const struct ddr_cali *cali, dramc_subsys_config *subsys);
void resetb_pull_dn(void);
void dramc_subsys_pre_config(dram_freq_grp freq_group, dramc_subsys_config *subsys);
void single_end_dramc_post_config(u8 lp4y_en);
void dram_configure(dram_freq_grp freq_group, dram_config *tr);
void ana_clk_div_config(ana_dvfs_core *tr, dvfs_group_config *dfs);
void apply_write_dbi_power_improve(bool onoff);
void dramc_write_dbi_onoff(u8 onoff);
void cbt_delay_ca_clk(u8 chn, u8 rank, s32 iDelay);
void dramc_cmd_ui_delay_setting(u8 chn, u8 value);
void dramc_dqsosc_set_mr18_mr19(const struct ddr_cali *cali,
u16 *osc_thrd_inc, u16 *osc_thrd_dec);
void dqsosc_shu_settings(const struct ddr_cali *cali,
u16 *osc_thrd_inc, u16 *osc_thrd_dec);
void shift_dq_ui(const struct ddr_cali *cali, u8 rk, s8 shift_ui);
void shuffle_dfs_to_fsp1(const struct ddr_cali *cali);
u8 get_cbt_vref_pinmux_value(const struct ddr_cali *cali, u8 range, u8 vref_lev);
void o1_path_on_off(const struct ddr_cali *cali, o1_state o1);
#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PI_API_H__ */

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src/soc/mediatek/mt8192/include/soc/dramc_register.h
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src/soc/mediatek/mt8192/include/soc/dramc_register_bits_def.h
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1
src/vendorcode/Makefile.inc
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@ -4,3 +4,4 @@ subdirs-y += intel
subdirs-y += siemens subdirs-y += siemens
subdirs-y += cavium subdirs-y += cavium
subdirs-y += eltan subdirs-y += eltan
subdirs-y += mediatek