soc/intel/{adl, common}: provide a list of D-states to enter LPM
This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Eran Mitrani
committed by
Martin Roth
Martin Roth
parent
d27cd2a328
commit
4c9440c673
@@ -51,6 +51,7 @@ enum acpi_device_sleep_states {
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ACPI_DEVICE_SLEEP_D3 = 3,
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ACPI_DEVICE_SLEEP_D3_HOT = ACPI_DEVICE_SLEEP_D3,
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ACPI_DEVICE_SLEEP_D3_COLD = 4,
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ACPI_DEVICE_SLEEP_NONE = 5,
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};
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#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
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@@ -1283,7 +1284,6 @@ typedef struct acpi_einj {
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acpi_einj_action_table_t action_table[ACTION_COUNT];
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} __packed acpi_einj_t;
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uintptr_t get_coreboot_rsdp(void);
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void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions);
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@@ -1298,8 +1298,6 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id);
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void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length);
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void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt);
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void soc_lpi_get_constraints(void *unused);
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void acpi_fill_fadt(acpi_fadt_t *fadt);
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void arch_fill_fadt(acpi_fadt_t *fadt);
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void soc_fill_fadt(acpi_fadt_t *fadt);
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@@ -22,13 +22,6 @@
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#include <cpu/cpu.h>
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#include <types.h>
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#define DEFAULT_CPU_D_STATE D0
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#define LPI_STATES_ALL 0xff
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#define LPI_REVISION 0
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#define LPI_ENABLED 1
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/*
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* List of supported C-states in this processor.
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*/
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@@ -119,14 +112,6 @@ static int cstate_set_s0ix[] = {
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C_STATE_C10
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};
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enum dev_sleep_states {
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D0, /* 0 */
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D1, /* 1 */
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D2, /* 2 */
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D3, /* 3 */
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NONE
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};
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const acpi_cstate_t *soc_get_cstate_map(size_t *entries)
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{
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static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
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@@ -181,156 +166,68 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
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fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
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}
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static const struct {
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uint8_t pci_dev;
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enum dev_sleep_states min_sleep_state;
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} min_pci_sleep_states[] = {
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{ SA_DEVFN_ROOT, D3 },
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{ SA_DEVFN_CPU_PCIE1_0, D3 },
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{ SA_DEVFN_IGD, D3 },
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{ SA_DEVFN_DPTF, D3 },
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{ SA_DEVFN_IPU, D3 },
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{ SA_DEVFN_CPU_PCIE6_0, D3 },
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{ SA_DEVFN_CPU_PCIE6_2, D3 },
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{ SA_DEVFN_TBT0, D3 },
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{ SA_DEVFN_TBT1, D3 },
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{ SA_DEVFN_TBT2, D3 },
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{ SA_DEVFN_TBT3, D3 },
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{ SA_DEVFN_GNA, D3 },
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{ SA_DEVFN_TCSS_XHCI, D3 },
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{ SA_DEVFN_TCSS_XDCI, D3 },
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{ SA_DEVFN_TCSS_DMA0, D3 },
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{ SA_DEVFN_TCSS_DMA1, D3 },
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{ SA_DEVFN_VMD, D3 },
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{ PCH_DEVFN_I2C6, D3 },
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{ PCH_DEVFN_I2C7, D3 },
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{ PCH_DEVFN_THC0, D3 },
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{ PCH_DEVFN_THC1, D3 },
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{ PCH_DEVFN_XHCI, D3 },
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{ PCH_DEVFN_USBOTG, D3 },
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{ PCH_DEVFN_SRAM, D3 },
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{ PCH_DEVFN_CNVI_WIFI, D3 },
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{ PCH_DEVFN_I2C0, D3 },
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{ PCH_DEVFN_I2C1, D3 },
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{ PCH_DEVFN_I2C2, D3 },
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{ PCH_DEVFN_I2C3, D3 },
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{ PCH_DEVFN_CSE, D0 },
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{ PCH_DEVFN_SATA, D3 },
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{ PCH_DEVFN_I2C4, D3 },
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{ PCH_DEVFN_I2C5, D3 },
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{ PCH_DEVFN_UART2, D3 },
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{ PCH_DEVFN_PCIE1, D0 },
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{ PCH_DEVFN_PCIE2, D0 },
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{ PCH_DEVFN_PCIE3, D0 },
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{ PCH_DEVFN_PCIE4, D0 },
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{ PCH_DEVFN_PCIE5, D0 },
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{ PCH_DEVFN_PCIE6, D0 },
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{ PCH_DEVFN_PCIE7, D0 },
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{ PCH_DEVFN_PCIE8, D0 },
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{ PCH_DEVFN_PCIE9, D0 },
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{ PCH_DEVFN_PCIE10, D0 },
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{ PCH_DEVFN_PCIE11, D0 },
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{ PCH_DEVFN_PCIE12, D0 },
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{ PCH_DEVFN_UART0, D3 },
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{ PCH_DEVFN_UART1, D3 },
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{ PCH_DEVFN_GSPI0, D3 },
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{ PCH_DEVFN_GSPI1, D3 },
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{ PCH_DEVFN_ESPI, D0 },
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{ PCH_DEVFN_PMC, D0 },
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{ PCH_DEVFN_HDA, D0 },
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{ PCH_DEVFN_SPI, D3 },
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{ PCH_DEVFN_GBE, D3 },
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static struct min_sleep_state min_pci_sleep_states[] = {
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{ SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_DPTF, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_CPU_PCIE6_0, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_CPU_PCIE6_2, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TBT0, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TBT1, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TBT2, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TBT3, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TCSS_XHCI, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TCSS_XDCI, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TCSS_DMA0, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_TCSS_DMA1, ACPI_DEVICE_SLEEP_D3 },
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{ SA_DEVFN_VMD, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C6, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C7, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_THC0, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_THC1, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_SRAM, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_CNVI_WIFI, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 },
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{ PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 },
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{ PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 },
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};
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static enum dev_sleep_states get_min_sleep_state(const struct device *dev)
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struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
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{
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if (!is_dev_enabled(dev))
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return NONE;
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switch (dev->path.type) {
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case DEVICE_PATH_APIC:
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return DEFAULT_CPU_D_STATE;
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case DEVICE_PATH_PCI:
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/* skip external buses*/
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if (dev->bus->secondary != 0)
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return NONE;
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for (size_t i = 0; i < ARRAY_SIZE(min_pci_sleep_states); i++)
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if (min_pci_sleep_states[i].pci_dev == dev->path.pci.devfn)
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return min_pci_sleep_states[i].min_sleep_state;
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printk(BIOS_WARNING, "Unknown min d_state for %x\n", dev->path.pci.devfn);
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return NONE;
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default:
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return NONE;
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}
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}
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/* Generate the LPI constraint table and return the number of devices included */
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void soc_lpi_get_constraints(void *unused)
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{
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unsigned int num_entries;
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const struct device *dev;
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enum dev_sleep_states min_sleep_state;
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num_entries = 0;
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for (dev = all_devices; dev; dev = dev->next) {
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if (get_min_sleep_state(dev) != NONE)
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num_entries++;
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}
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acpigen_emit_byte(RETURN_OP);
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acpigen_write_package(num_entries);
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size_t cpu_index = 0;
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for (dev = all_devices; dev; dev = dev->next) {
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min_sleep_state = get_min_sleep_state(dev);
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if (min_sleep_state == NONE)
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continue;
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acpigen_write_package(3);
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{
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char path[32] = { 0 };
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/* Emit the device path */
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switch (dev->path.type) {
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case DEVICE_PATH_PCI:
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acpigen_emit_namestring(acpi_device_path(dev));
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break;
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case DEVICE_PATH_APIC:
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snprintf(path, sizeof(path), CONFIG_ACPI_CPU_STRING,
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cpu_index++);
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acpigen_emit_namestring(path);
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break;
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default:
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/* Unhandled */
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printk(BIOS_WARNING,
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"Unhandled device path type %d\n", dev->path.type);
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acpigen_emit_namestring(NULL);
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break;
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}
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acpigen_write_integer(LPI_ENABLED);
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acpigen_write_package(2);
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{
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acpigen_write_integer(LPI_REVISION);
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acpigen_write_package(2); /* no optional device info */
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{
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/* Assume constraints apply to all entries */
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acpigen_write_integer(LPI_STATES_ALL);
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acpigen_write_integer(min_sleep_state); /* min D-state */
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}
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acpigen_write_package_end();
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}
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acpigen_write_package_end();
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}
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acpigen_write_package_end();
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}
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acpigen_write_package_end();
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printk(BIOS_INFO, "Returning SoC specific constraint package for %d devices\n", num_entries);
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*size = ARRAY_SIZE(min_pci_sleep_states);
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return min_pci_sleep_states;
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}
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uint32_t soc_read_sci_irq_select(void)
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@@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <acpi/acpi.h>
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#include <acpi/acpi_pm.h>
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#include <acpi/acpigen.h>
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#include <arch/ioapic.h>
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@@ -69,7 +70,6 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current)
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current +=
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acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
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return current;
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}
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@@ -23,10 +23,20 @@
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#define RESTORE_PM_BITS_HOOK "\\_SB.PCI0.RGPM"
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#define THUNDERBOLT_DEVICE "\\_SB.PCI0.TXHC"
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#define THUNDERBOLT_IOM_DPOF "\\_SB.PCI0.DPOF"
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#define LPI_STATES_ALL 0xff
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#define MIN_DEVICE_STATE ACPI_DEVICE_SLEEP_D0
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#define PEPD_SCOPE "\\_SB.PCI0"
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#define MIN_DEVICE_STATE ACPI_DEVICE_SLEEP_D0
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#define LPI_STATES_ALL 0xff
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enum {
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LPI_REVISION_0 = 0,
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};
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enum {
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LPI_DISABLED = 0,
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LPI_ENABLED = 1,
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};
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struct reg_info {
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uint8_t *addr;
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size_t buffer_size;
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@@ -81,7 +91,7 @@ static void read_pmc_lpm_requirements(const struct soc_pmc_lpm *lpm,
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* device, one that is known to exist, i.e. ACPI_CPU_STRING. expects at least
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* one device and crashes without it with a bluescreen.
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*/
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__weak void soc_lpi_get_constraints(void *unused)
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static void acpi_gen_default_lpi_constraints(void)
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{
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char path[16];
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printk(BIOS_INFO, "Returning default LPI constraint package\n");
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@@ -117,6 +127,110 @@ __weak void soc_lpi_get_constraints(void *unused)
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acpigen_write_package_end();
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}
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__weak struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
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{
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printk(BIOS_DEBUG, "Empty min sleep state array returned\n");
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*size = 0;
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return NULL;
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}
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static enum acpi_device_sleep_states get_min_sleep_state(
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const struct device *dev, struct min_sleep_state *states_arr, size_t size)
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{
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if (!is_dev_enabled(dev))
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return ACPI_DEVICE_SLEEP_NONE;
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switch (dev->path.type) {
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case DEVICE_PATH_APIC:
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return MIN_DEVICE_STATE;
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case DEVICE_PATH_PCI:
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/* skip external buses*/
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if ((dev->bus->secondary != 0) || (!states_arr))
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return ACPI_DEVICE_SLEEP_NONE;
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for (size_t i = 0; i < size; i++)
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if (states_arr[i].pci_dev == dev->path.pci.devfn)
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return states_arr[i].min_sleep_state;
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printk(BIOS_WARNING, "Unknown min d_state for %x\n", dev->path.pci.devfn);
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return ACPI_DEVICE_SLEEP_NONE;
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default:
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return ACPI_DEVICE_SLEEP_NONE;
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}
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}
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/* Generate the LPI constraint table */
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static void acpi_lpi_get_constraints(void *unused)
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{
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unsigned int num_entries = 0;
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const struct device *dev;
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enum acpi_device_sleep_states min_sleep_state;
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size_t size;
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struct min_sleep_state *states_arr = soc_get_min_sleep_state_array(&size);
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if (size && states_arr) {
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for (dev = all_devices; dev; dev = dev->next) {
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if (get_min_sleep_state(dev, states_arr, size)
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!= ACPI_DEVICE_SLEEP_NONE)
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num_entries++;
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}
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}
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if (!num_entries) {
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acpi_gen_default_lpi_constraints();
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} else {
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acpigen_emit_byte(RETURN_OP);
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acpigen_write_package(num_entries);
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size_t cpu_index = 0;
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for (dev = all_devices; dev; dev = dev->next) {
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min_sleep_state = get_min_sleep_state(dev, states_arr, size);
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if (min_sleep_state == ACPI_DEVICE_SLEEP_NONE)
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continue;
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acpigen_write_package(3);
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{
|
||||
char path[32] = { 0 };
|
||||
/* Emit the device path */
|
||||
switch (dev->path.type) {
|
||||
case DEVICE_PATH_PCI:
|
||||
acpigen_emit_namestring(acpi_device_path(dev));
|
||||
break;
|
||||
|
||||
case DEVICE_PATH_APIC:
|
||||
snprintf(path, sizeof(path), CONFIG_ACPI_CPU_STRING,
|
||||
cpu_index++);
|
||||
acpigen_emit_namestring(path);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Unhandled */
|
||||
printk(BIOS_WARNING,
|
||||
"Unhandled device path type %d\n",
|
||||
dev->path.type);
|
||||
acpigen_emit_namestring(NULL);
|
||||
break;
|
||||
}
|
||||
|
||||
acpigen_write_integer(LPI_ENABLED);
|
||||
acpigen_write_package(2);
|
||||
{
|
||||
acpigen_write_integer(LPI_REVISION_0);
|
||||
acpigen_write_package(2); /* no optional device info */
|
||||
{
|
||||
/* Assume constraints apply to all entries */
|
||||
acpigen_write_integer(LPI_STATES_ALL);
|
||||
/* min D-state */
|
||||
acpigen_write_integer(min_sleep_state);
|
||||
}
|
||||
acpigen_write_package_end();
|
||||
}
|
||||
acpigen_write_package_end();
|
||||
}
|
||||
acpigen_write_package_end();
|
||||
}
|
||||
acpigen_write_package_end();
|
||||
}
|
||||
}
|
||||
|
||||
static void lpi_s0ix_entry(void *unused)
|
||||
{
|
||||
/* Inform the EC */
|
||||
@@ -200,7 +314,7 @@ static void lpi_display_off(void *unused)
|
||||
|
||||
static void (*lpi_s0_helpers[])(void *) = {
|
||||
NULL, /* enumerate functions (autogenerated) */
|
||||
soc_lpi_get_constraints,/* get device constraints */
|
||||
acpi_lpi_get_constraints,/* get device constraints */
|
||||
NULL, /* get crash dump device */
|
||||
lpi_display_off, /* display off notify */
|
||||
lpi_display_on, /* display on notify */
|
||||
|
||||
@@ -127,4 +127,31 @@ enum core_type get_soc_cpu_type(void);
|
||||
|
||||
/* Check if CPU supports Nominal frequency or not */
|
||||
bool soc_is_nominal_freq_supported(void);
|
||||
|
||||
/* Min sleep state per device*/
|
||||
struct min_sleep_state {
|
||||
uint8_t pci_dev;
|
||||
enum acpi_device_sleep_states min_sleep_state;
|
||||
};
|
||||
|
||||
/*
|
||||
* This SOC callback returns an array that maps devices to their min sleep state.
|
||||
* Example:
|
||||
*
|
||||
* static struct min_sleep_state min_pci_sleep_states[] = {
|
||||
* { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 },
|
||||
* { SA_DEVFN_CPU_PCIE1_0, ACPI_DEVICE_SLEEP_D3 },
|
||||
* { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 },
|
||||
* ...
|
||||
* };
|
||||
*
|
||||
* const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
* {
|
||||
* *num = ARRAY_SIZE(early_gpio_table);
|
||||
* return early_gpio_table;
|
||||
* }
|
||||
*
|
||||
*/
|
||||
struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size);
|
||||
|
||||
#endif /* _SOC_INTEL_COMMON_BLOCK_ACPI_H_ */
|
||||
|
||||
Reference in New Issue
Block a user