Fix the static device tree of the Tyan S1846. Especially the
Super I/O part was incorrect. Also, add ide0_enable/ide1_enable variables, and enable both the primary and secondary IDE interface per default. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -125,38 +125,46 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
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dir /pc80
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config chip.h
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# TODO.
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chip northbridge/intel/i440bx # Northbridge
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device pci_domain 0 on
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device pci 0.0 on end # Host bridge
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device pci 1.0 off end # PCI bridge TODO: AGP bridge?
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# device pci 7.0 on end # ISA bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge ???
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chip superio/nsc/pc87309 # Super I/O
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device pnp 2e.0 on end # Floppy
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device pnp 2e.1 on end # Parallel port
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device pnp 2e.2 on end # Com2
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device pnp 2e.3 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 on end # Power mgmt.
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device pnp 2e.5 on end # Mouse
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12 # ???
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end
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end
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.3 on end # ACPI
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end
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end
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end
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chip cpu/intel/slot_2
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end
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chip northbridge/intel/i440bx # Northbridge
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device pci_domain 0 on
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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chip superio/nsc/pc87309 # Super I/O
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device pnp 2e.5 on # Keyboard + Mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.b on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.c on # Com2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.d on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.f on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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end
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end
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device pci 7.1 on end # IDE
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device pci 7.2 on end # USB
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device pci 7.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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end
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end
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chip cpu/intel/slot_2 # CPU
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end
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end
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