lib/spd_bin: Cleanup spd_get_banks
Remove the switch case in spd_get_banks. The LPDDR4X adapt DDR4 attributes. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Icfaefd1856d2350c6e5a91d233ccdb10d5259391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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		| @@ -76,22 +76,15 @@ static int spd_get_banks(const uint8_t spd[], int dram_type) | |||||||
| 	static const int ddr3_banks[4] = { 8, 16, 32, 64 }; | 	static const int ddr3_banks[4] = { 8, 16, 32, 64 }; | ||||||
| 	static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; | 	static const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; | ||||||
| 	int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; | 	int index = (spd[SPD_DENSITY_BANKS] >> 4) & 0xf; | ||||||
| 	switch (dram_type) { |  | ||||||
| 	/* DDR3 and LPDDR3_Intel have the same bank definition */ | 	if (use_ddr4_params(dram_type)) { | ||||||
| 	case SPD_DRAM_DDR3: |  | ||||||
| 	case SPD_DRAM_LPDDR3_INTEL: |  | ||||||
| 		if (index >= ARRAY_SIZE(ddr3_banks)) |  | ||||||
| 			return -1; |  | ||||||
| 		return ddr3_banks[index]; |  | ||||||
| 	/* LPDDR3, LPDDR4 and DDR4 have the same bank definition */ |  | ||||||
| 	case SPD_DRAM_LPDDR3_JEDEC: |  | ||||||
| 	case SPD_DRAM_DDR4: |  | ||||||
| 	case SPD_DRAM_LPDDR4: |  | ||||||
| 		if (index >= ARRAY_SIZE(ddr4_banks)) | 		if (index >= ARRAY_SIZE(ddr4_banks)) | ||||||
| 			return -1; | 			return -1; | ||||||
| 		return ddr4_banks[index]; | 		return ddr4_banks[index]; | ||||||
| 	default: | 	} else { | ||||||
|  | 		if (index >= ARRAY_SIZE(ddr3_banks)) | ||||||
| 			return -1; | 			return -1; | ||||||
|  | 		return ddr3_banks[index]; | ||||||
| 	} | 	} | ||||||
| } | } | ||||||
|  |  | ||||||
|   | |||||||
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