payloads/external/SeaBIOS: Allow setting buffers below 0xC0000

Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
This is a requirement on the Intel Rangeley processor
because it is designed so that only the processor can write
the higher memory areas.  This prevents USB and SATA from bus-mastering
into the buffers when they're set in the typical 0xE0000 area.

This will be set to Y unless defaulted to N by the mainboard or
chipset.

Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak

Change-Id: I15638605d1c66a2277d4b852796db89978551a34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

src/Kconfig

@@ -623,6 +623,19 @@ config SEABIOS_THREAD_OPTIONROMS
 	  variations during option ROM code execution. It is not
 	  known if all option ROMs will behave properly with this option.
 
+config SEABIOS_MALLOC_UPPERMEMORY
+	bool
+	default y
+	depends on PAYLOAD_SEABIOS
+	help
+	  Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal
+	  "low memory" allocations.  If this is not selected, the memory is
+	  instead allocated from the "9-segment" (0x90000-0xa0000).
+	  This is not typically needed, but may be required on some platforms
+	  to allow USB and SATA buffers to be written correctly by the
+	  hardware.  In general, if this is desired, the option will be
+	  set to 'N' by the chipset Kconfig.
+
 choice
 	prompt "GRUB2 version"
 	default GRUB2_MASTER