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payloads/external/SeaBIOS: Allow setting buffers below 0xC0000

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Add the option to coreboot to set the SeaBIOS buffers below 0xC0000.
This is a requirement on the Intel Rangeley processor
because it is designed so that only the processor can write
the higher memory areas.  This prevents USB and SATA from bus-mastering
into the buffers when they're set in the typical 0xE0000 area.

This will be set to Y unless defaulted to N by the mainboard or
chipset.

Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak

Change-Id: I15638605d1c66a2277d4b852796db89978551a34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth
2014-07-25 14:39:05 -06:00
committed by Martin Roth
parent b3997ba6f2
commit 4d7d25f38a
4 changed files with 25 additions and 0 deletions
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1
src/arch/x86/Makefile.inc
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@@ -351,6 +351,7 @@ seabios:
CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \
CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \
CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \
CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \
OUT=$(abspath $(obj)) IASL="$(IASL)"
filo: