Rename documentation -> Documentation
In order to be closer to the Linux kernel source tree structure, rename documentation to Documentation. Change-Id: I8690f666638ef352d201bd3c3dc1923b0d24cb12 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10110 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Stefan Reinauer
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Documentation/AMD-S3.txt
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_____ ____ _____ ______ ____ ____ ____ _______
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/ ____/ __ \| __ \| ____| _ \ / __ \ / __ \__ __|
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| | | | | | |__) | |__ | |_) | | | | | | | | |
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| | | | | | _ /| __| | _ <| | | | | | | | |
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| |___| |__| | | \ \| |____| |_) | |__| | |__| | | |
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\_____\____/|_| \_\______|____/ \____/ \____/ |_|
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__ __ _____ _____ ____
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/\ | \/ | __ \ / ____| |___ \
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/ \ | \ / | | | | | (___ __) |
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/ /\ \ | |\/| | | | | \___ \ |__ <
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/ ____ \| | | | |__| | ____) | ___) |
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/_/ \_\_| |_|_____/ |_____/ |____/
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S3 in Coreboot (V 1.2)
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----------------------------------------
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Zheng Bao
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<zheng.bao@amd.com>
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<fishbaozi@gmail.com>
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Introduction
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============
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This document is about how the feature S3 is implemented on coreboot,
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specifically on AMD platform. This topic deals with ACPI spec, hardware,
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BIOS, OS. We try to help coreboot users to realize their own S3.
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S3 in a nutshell
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================
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The S3 sleeping state is a low wake latency sleeping state where all
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system context is lost except system memory. [1]. S3 is a ACPI
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definition.
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To enter S3, write 3 in SLP_TYPx and set the SLP_EN bit (See ACPI
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registers). But if you do that, board can not resume at where it
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sleeps, because you don't save the context. More often than not, we
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make the board go into S3 by the tools which OSes provide. For
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windows, click Start->sleep. For linux, some distribution provide a
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tools called pm-suspend, which can make the system goto S3. If
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pm-suspend is not available, we can run "echo mem > /sys/power/state",
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but this way may not save all the needed context.
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In S3 state, the power is off. So when the power button is pressed,
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BIOS runs as it does in cold boot. If BIOS didn't detect whether
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board boots or resumes, it would go the same way as boot. It is not
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what we expect. BIOS detects the SLP_TYPx. If it is 3, it means BIOS
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are waking up.
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BIOS is responsible for restore the machine state as it is before
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sleep. It needs restore the memory controller, not overwriting memory
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which is not marked as reserved. For the peripheral which loses its
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registers, BIOS needs to write the original value.
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When everything is done, BIOS needs to find out the wakeup vector
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provided by OSes and jump there. OSes also have work to do. We can go
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to linux kernel or some other open source projects to find out how they
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handle S3 resume.
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ACPI registers
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==============
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ACPI specification defines a group of registers. OSes handle all these
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registers to read and write status to all the platform.
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On AMD platform, these registers are provided by southbridge. For
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example, Hudson uses PMIO 60:6F to define ACPI registers.
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OSes don't have any specific driver to know where these registers
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are. BIOS has the responsibility to allocated the IO resources and
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write all these address to FADT, a ACPI defined table.
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Memory Layout
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=============
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Restoring memory is the most important job done by BIOS. When the
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power is off, the memory is maintained by standby power. BIOS need to
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make sure that when flow goes to OS, everything in memory should be
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the same as it was.
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The chip vendor will provide a way, or code, to wake up the memory
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from sleeping. In AGESA 2008 arch, it is called AmdInitResume.
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The BIOS itself needs some memory to run. Either, BIOS marks the erea
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as reserved in e820, or BIOS saves the content into reserved space.
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Here is the address Map for S3 Resume. Assumingly the total memory is 1GB.
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00000000 --- 00100000 BIOS Reserved area.
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00100000 --- 00200000 Free
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00200000 --- 01000000 Coreboot ramstage area.
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01000000 --- 2e160000 Free
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2e160000 --- 2e170000 ACPI table
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2e170000 --- 2ef70000 OSRAM
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2ef70000 --- 2efe0000 Stack in highmem
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2efe0000 --- 2f000000 heap in highmem
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2f000000 TOM
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AMD requirements in S3
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======================
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Chip vendor like AMD will provide bunch of routines to restore the
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board.[2]
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* AmdS3Save: It is called in cold boot, save required register into
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non-volatile storage. Currently, we use SPI flash to store the data.
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* AmdInitResume: Restore the memory controller.
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* AmdS3LateRestore: Called after AmdInitResume, restore other
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register that memory.
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* (SouthBridge)InitS3EarlyRestore, (SouthBridge)InitS3LateRestore:
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Provided by Southbridge vendor code. Early is called before PCI
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enumeration, and Late is called after that.
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Lifecycle of booting, sleeping and waking Coreboot and Ubuntu
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=============================================================
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1. Cold boot.
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For a system with S3 feature, the BIOS needs to save some data to
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non-volatile storage at cold boot stage. What data need to be save are
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provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets
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the VolatileStorage and NvStorage, which are where the data are
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located. It is the wrappers's responsibility to save the data.[3][4]
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Currently, the wrappers allocate a CBFS modules in BIOS image. To do
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that, the wrapper needs to have the ability to write flash chips. It
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is not as comprehensive as flashrom. But for the SST chip on Parmer,
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MX chip on Thather, coreboot works well.[5]
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2. OS goes in S3.
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For Linux, besides the kernel needs to do some saving, most distributions
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run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d.
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# ls /usr/lib/pm-utils/sleep.d
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000kernel-change 49bluetooth 90clock 95led
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00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler
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00powersave 60_wpa_supplicant 95anacron 99video
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01PulseAudio 75modules 95hdparm-apm
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The script with lower prefix runs before the one with higher prefix.
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99video is the last one.
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Those scripts have hooks called hibernate, suspend, thaw, resume. For
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each script, suspend is called when system sleeps and wakeup is called
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when system wakeups.
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3. Firmware detects S3 wakeup
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As we mentioned, Firmware detects the SLP_TYPx to find out if the board
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wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called
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as they are during cold boot. AmdInitResume and AmdS3LateRestore are
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called only during resume. For whole ramstage, Coreboot goes through
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almost the same way as cold boot, other than not calling the AmdInitMid,
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AmdInitLate and AmdS3Save, and restoring all the MTRRs.
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At last step of coreboot stage, coreboot finds out the wakeup vector in FADT,
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written by OS, and jump.
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4. OS resumes.
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When Linux resumes, all the sleeping scripts call their resume
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hooks. If we are more lucky, all the scripts can go through. More
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chances that the 99video hangs or fails to get the display
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back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in
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Coreboot/Kconfig. That needs more troubleshooting.
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Reference
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=========
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[1] ACPI40a, http://www.acpi.info/spec40a.htm
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[2] Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/
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[3] Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c
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[4] Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c
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[5] Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c
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1797
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# Doxyfile 1.8.8
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\documentclass[10pt,letterpaper]{article}
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|
||||
\usepackage{amsmath}
|
||||
\usepackage{amsfonts}
|
||||
\usepackage{amssymb}
|
||||
\author{Ron Minnich}
|
||||
\title{Kconfig usage in coreboot v2}
|
||||
\begin{document}
|
||||
\section{Introduction}
|
||||
This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them.
|
||||
\section{Kconfig variations}
|
||||
Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard.
|
||||
|
||||
For variables set by the user, see src/console/Kconfig.
|
||||
|
||||
For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent.
|
||||
|
||||
Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
|
||||
|
||||
\section{Makefile and Makefile.inc}
|
||||
There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y.
|
||||
|
||||
Make is not recursive. There is only one make process.
|
||||
\subsection{subdirs usage}
|
||||
Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y.
|
||||
|
||||
We define the common rules for which variation to use below.
|
||||
\subsection{object file specification}
|
||||
There are several different types of objects specified in the tree. They are:
|
||||
\begin{description}
|
||||
\item[obj]objects for the ram part of the code
|
||||
\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
|
||||
\item[initobj]seperately-compiled code for the ROM section of coreboot
|
||||
\end{description}
|
||||
These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
|
||||
|
||||
\section{Example: AMD serengeti cheetah}
|
||||
\subsection{mainboard/Kconfig}
|
||||
Defines Vendor variables. Currently defined variables are:
|
||||
Sources all Kconfig files in the vendor directories.
|
||||
\input{ mainboardkconfig.tex}
|
||||
\subsection{mainboard/Makefile.inc}
|
||||
There is none at this time.
|
||||
\subsection{mainboard/$<$vendor$>$/Kconfig}
|
||||
We use the amd as a model. The only action currently taken is to source all Kconfig's in the
|
||||
subdirectories.
|
||||
\subsection{mainboard/$<$vendor$>$/Makefile.inc}
|
||||
We use amd as a model. There is currently no Makefile.inc at this level.
|
||||
\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig}
|
||||
The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines
|
||||
and rules in here determine everything about how a mainboard target is built.
|
||||
We will use serengeti\_cheetah as a model. It defines these variables.
|
||||
\input{ mainboardkconfig.tex}
|
||||
\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc}
|
||||
This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece.
|
||||
Note that this is the mainboard as of August, 2009, and it may change over time.
|
||||
\subsubsection{objects}
|
||||
We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional:
|
||||
\begin{verbatim}
|
||||
driver-y += mainboard.o
|
||||
|
||||
#needed by irq_tables and mptable and acpi_tables
|
||||
obj-y += get_bus_conf.o
|
||||
obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
|
||||
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += fadt.o
|
||||
|
||||
#./ssdt.o is in northbridge/amd/amdk8/Config.lb
|
||||
obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt2.o
|
||||
obj-$(CONFIG_ACPI_SSDTX_NUM) += ssdt3.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += ssdt4.o
|
||||
driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
|
||||
|
||||
# This is part of the conversion to init-obj and away from included code.
|
||||
|
||||
initobj-y += crt0.o
|
||||
\end{verbatim}
|
||||
\subsubsection{romcc legacy support}
|
||||
We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define
|
||||
crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the
|
||||
old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally.
|
||||
\begin{verbatim}
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
|
||||
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
|
||||
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
|
||||
crt0-y += ../../../../src/arch/i386/lib/id.inc
|
||||
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
|
||||
crt0-y += auto.inc
|
||||
|
||||
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
|
||||
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/id.lds
|
||||
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
|
||||
|
||||
\end{verbatim}
|
||||
\subsubsection{POST\_EVALUATION}
|
||||
POST\_EVALUATION rules should be placed after this section:
|
||||
\begin{verbatim}
|
||||
ifdef POST_EVALUATION
|
||||
\end{verbatim}
|
||||
to ensure that the values of variables are correct.
|
||||
Here are the post-evaluation rules for this mainboard:
|
||||
\begin{verbatim}
|
||||
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
|
||||
iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
|
||||
mv dsdt.hex $@
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
|
||||
|
||||
$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
|
||||
iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
|
||||
mv pci2.hex ssdt2.c
|
||||
|
||||
$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
|
||||
iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
|
||||
mv pci3.hex ssdt3.c
|
||||
|
||||
$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
|
||||
iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
|
||||
perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
|
||||
mv pci4.hex ssdt4.c
|
||||
|
||||
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
|
||||
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
|
||||
perl -e 's/\.rodata/.rom.data/g' -pi $@
|
||||
perl -e 's/\.text/.section .rom.text/g' -pi $@
|
||||
|
||||
\end{verbatim}
|
||||
The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables.
|
||||
\subsubsection{devicetree.cb}
|
||||
Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
|
||||
properly, as it defines topology and chips that can be defined no other way.
|
||||
Let's go through the tree.
|
||||
\begin{verbatim}
|
||||
chip northbridge/amd/amdk8/root_complex
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/amd/socket_F
|
||||
device lapic 0 on end
|
||||
end
|
||||
end
|
||||
\end{verbatim}
|
||||
This topology is always somewhat confusing to newcomers, and even to coreboot veterans.
|
||||
|
||||
We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we
|
||||
have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
|
||||
somewhere, since it runs memory.
|
||||
|
||||
|
||||
What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
|
||||
CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains
|
||||
its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
|
||||
{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on,
|
||||
which connects to a {\it cpu/amd/socket\_F},
|
||||
which has a local apic, which is on.
|
||||
|
||||
Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
|
||||
is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
|
||||
BIOSes) that the BSP be CPU 0; any CPU will do.
|
||||
\begin{verbatim}
|
||||
device domain 0 on
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 18.0 on # northbridge
|
||||
# devices on link 0, link 0 == LDT 0
|
||||
\end{verbatim}
|
||||
Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On
|
||||
Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up.
|
||||
\begin{verbatim}
|
||||
chip southbridge/amd/amd8132
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 1.0 on end
|
||||
device pci 1.1 on end
|
||||
end
|
||||
\end{verbatim}
|
||||
This is the 8132, a bridge to a secondary PCI bus.
|
||||
\begin{verbatim}
|
||||
chip southbridge/amd/amd8111
|
||||
# this "device pci 0.0" is the parent the next one
|
||||
# PCI bridge
|
||||
device pci 0.0 on
|
||||
device pci 0.0 on end
|
||||
device pci 0.1 on end
|
||||
device pci 0.2 off end
|
||||
device pci 1.0 off end
|
||||
end
|
||||
\end{verbatim}
|
||||
The 8111 is a bridge to other busses and to the legacy ISA devices such as superio.
|
||||
\begin{verbatim}
|
||||
device pci 1.0 on
|
||||
chip superio/winbond/w83627hf
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.6 off # CIR
|
||||
io 0x60 = 0x100
|
||||
end
|
||||
device pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
io 0x60 = 0x220
|
||||
io 0x62 = 0x300
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.8 off end # GPIO2
|
||||
device pnp 2e.9 off end # GPIO3
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
irq 0x70 = 5
|
||||
end
|
||||
end
|
||||
end
|
||||
\end{verbatim}
|
||||
The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the
|
||||
2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN.
|
||||
\begin{verbatim}
|
||||
device pci 1.1 on end
|
||||
device pci 1.2 on end
|
||||
\end{verbatim}
|
||||
More devices. These statements set up placeholders in the device tree.
|
||||
\begin{verbatim}
|
||||
device pci 1.3 on
|
||||
chip drivers/i2c/i2cmux # pca9556 smbus mux
|
||||
device i2c 18 on #0 pca9516 1
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
end
|
||||
device i2c 18 on #1 pca9516 2
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-2-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-2-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-3-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-3-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # acpi
|
||||
\end{verbatim}
|
||||
These are the i2c devices.
|
||||
\begin{verbatim}
|
||||
device pci 1.5 off end
|
||||
device pci 1.6 off end
|
||||
\end{verbatim}
|
||||
More placeholders.
|
||||
\begin{verbatim}
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end # device pci 18.0
|
||||
|
||||
\end{verbatim}
|
||||
These "register" commands set controls in the southbridge.
|
||||
\begin{verbatim}
|
||||
device pci 18.0 on end
|
||||
device pci 18.0 on end
|
||||
\end{verbatim}
|
||||
These are the other two hypertransport links.
|
||||
\begin{verbatim}
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
\end{verbatim}
|
||||
The 18.1 devices are, again, northbridge control for various k8 functions.
|
||||
\begin{verbatim}
|
||||
end
|
||||
\end{verbatim}
|
||||
That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here.
|
||||
\begin{verbatim}
|
||||
chip northbridge/amd/amdk8
|
||||
device pci 19.0 on # northbridge
|
||||
chip southbridge/amd/amd8151
|
||||
# the on/off keyword is mandatory
|
||||
device pci 0.0 on end
|
||||
device pci 1.0 on end
|
||||
end
|
||||
end # device pci 19.0
|
||||
|
||||
device pci 19.0 on end
|
||||
device pci 19.0 on end
|
||||
device pci 19.1 on end
|
||||
device pci 19.2 on end
|
||||
device pci 19.3 on end
|
||||
end
|
||||
|
||||
|
||||
\end{verbatim}
|
||||
|
||||
\subsection{cpu socket}
|
||||
The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only
|
||||
the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus
|
||||
of all defines and Makefile controls for building the CPU components of a board.
|
||||
|
||||
\subsubsection{ cpu/Kconfig}
|
||||
Defines variables. Current variables are:
|
||||
\input{cpukconfig.tex}
|
||||
Sources all Kconfig files in the vendor directories.
|
||||
\subsubsection{ cpu/Makefile.inc}
|
||||
Unconditionally sources all Makefile.inc in the vendor directories.
|
||||
|
||||
\subsection{cpu/$<$vendor$>$/Kconfig}
|
||||
The only action currently taken is to source all Kconfig's in the
|
||||
subdirectories.
|
||||
\subsection{cpu/$<$vendor$>$/Makefile.inc}
|
||||
{\em Conditionally} source the socket directories.
|
||||
Example:
|
||||
\begin{verbatim}
|
||||
subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
|
||||
\end{verbatim}
|
||||
.
|
||||
CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file.
|
||||
|
||||
\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig}
|
||||
Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that
|
||||
the socket, as much as possible, should control the models, because the models may plug into many sockets.
|
||||
Socket\_F currently sets:
|
||||
\input{socketfkconfig.tex}
|
||||
|
||||
It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced.
|
||||
|
||||
\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig}
|
||||
CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that
|
||||
if needed.
|
||||
\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc}
|
||||
The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional
|
||||
compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all}
|
||||
objects, because it is not possible to determine at build time what options may be needed for a given model CPU.
|
||||
This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc.
|
||||
|
||||
\subsection{northbridge}
|
||||
\subsubsection{northbridge/Kconfig}
|
||||
No variables. Source all vendor directory Kconfigs.
|
||||
\subsubsection{northbridge/Makefile.inc}
|
||||
No variables. unconditionally include all vendor Makefile.inc
|
||||
\subsubsection{northbridge/$<$vendor$>$/Kconfig}
|
||||
No variables. Source all chip directory Kconfigs.
|
||||
\subsubsection{northbridge/$<$vendor$>$/Makefile.inc}
|
||||
No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
|
||||
is the name of the part, e.g.
|
||||
\begin{verbatim}
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
|
||||
\end{verbatim}
|
||||
.
|
||||
\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
|
||||
Typically a small number of variables. One defines the part name. Here is an example
|
||||
of the variables defined for the K8.
|
||||
\begin{verbatim}
|
||||
config NORTHBRIDGE_AMD_AMDK8
|
||||
bool
|
||||
default n
|
||||
|
||||
config AGP_APERTURE_SIZE
|
||||
hex
|
||||
default 0x4000000
|
||||
\end{verbatim}
|
||||
\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
|
||||
Typically very small set of rules, and very simple.
|
||||
Since this file is already conditionally included,
|
||||
we don't need to test for the chipset CONFIG variable. We
|
||||
can therefore test other variables (which is part of the reason
|
||||
we set up conditional inclusion of this file, instead
|
||||
of unconditionally including it). Here is an example from AMD K8.
|
||||
Note that we can make a variable conditional on the ACPI tables.
|
||||
\begin{verbatim}
|
||||
driver-y += northbridge.o
|
||||
driver-y += misc_control.o
|
||||
obj-y += get_sblk_pci1234.o
|
||||
obj-$(CONFIG_HAVE_ACPI_TABLES) += amdk8_acpi.o
|
||||
\end{verbatim}
|
||||
|
||||
\subsection{southbridge}
|
||||
\subsubsection{southbridge/Kconfig}
|
||||
No variables. Source all vendor directory Kconfigs.
|
||||
\subsubsection{southbridge/Makefile.inc}
|
||||
No variables. {\em Unconditionally} include all vendor Makefile.inc
|
||||
\subsubsection{southbridge/$<$vendor$>$/Kconfig}
|
||||
No variables. Source all chip directory Kconfigs.
|
||||
\subsubsection{southbridge/$<$vendor$>$/Makefile.inc}
|
||||
No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
|
||||
is the name of the part, e.g.
|
||||
\begin{verbatim}
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
|
||||
\end{verbatim}
|
||||
.
|
||||
\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
|
||||
Typically a small number of variables. One defines the part name. Here is an example
|
||||
of the variables defined for the K8.
|
||||
\begin{verbatim}
|
||||
config SOUTHBRIDGE_AMD_AMD8111
|
||||
bool
|
||||
default n
|
||||
|
||||
\end{verbatim}
|
||||
\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
|
||||
Typically very small set of rules, and very simple.
|
||||
Since this file is already conditionally included,
|
||||
we don't need to test for the chipset CONFIG variable. We
|
||||
can therefore test other variables (which is part of the reason
|
||||
we set up conditional inclusion of this file, instead
|
||||
of unconditionally including it). Here is an example from AMD 8111.
|
||||
No conditionals in this one yet.
|
||||
\begin{verbatim}
|
||||
driver-y += amd8111.o
|
||||
driver-y += amd8111_usb.o
|
||||
driver-y += amd8111_lpc.o
|
||||
driver-y += amd8111_ide.o
|
||||
driver-y += amd8111_acpi.o
|
||||
driver-y += amd8111_usb2.o
|
||||
driver-y += amd8111_ac97.o
|
||||
driver-y += amd8111_nic.o
|
||||
driver-y += amd8111_pci.o
|
||||
driver-y += amd8111_smbus.o
|
||||
obj-y += amd8111_reset.o
|
||||
\end{verbatim}
|
||||
|
||||
\subsubsection{vendor and part}
|
||||
\subsection{southbridge}
|
||||
\subsubsection{vendor and part}
|
||||
\subsection{superio}
|
||||
\subsection{drivers/i2c}
|
||||
This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed.
|
||||
To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have:
|
||||
\begin{verbatim}
|
||||
\end{verbatim}
|
||||
|
||||
\subsubsection{vendor and part}
|
||||
|
||||
\end{document}
|
||||
71
Documentation/Makefile
Normal file
71
Documentation/Makefile
Normal file
@@ -0,0 +1,71 @@
|
||||
#
|
||||
# Makefile for coreboot paper.
|
||||
# hacked together by Stefan Reinauer <stepan@openbios.org>
|
||||
#
|
||||
|
||||
PDFLATEX=pdflatex -t a4
|
||||
|
||||
FIGS=codeflow.pdf hypertransport.pdf
|
||||
|
||||
all: CorebootPortingGuide.pdf Kconfig.pdf
|
||||
|
||||
SVG2PDF=$(shell which svg2pdf)
|
||||
INKSCAPE=$(shell which inkscape)
|
||||
CONVERT=$(shell which convert)
|
||||
|
||||
codeflow.pdf: codeflow.svg
|
||||
ifneq ($(strip $(SVG2PDF)),)
|
||||
svg2pdf $< $@
|
||||
else ifneq ($(strip $(INKSCAPE)),)
|
||||
inkscape $< --export-pdf=$@
|
||||
else ifneq ($(strip $(CONVERT)),)
|
||||
convert $< $@
|
||||
endif
|
||||
|
||||
hypertransport.pdf: hypertransport.svg
|
||||
ifneq ($(strip $(SVG2PDF)),)
|
||||
svg2pdf $< $@
|
||||
else ifneq ($(strip $(INKSCAPE)),)
|
||||
inkscape $< --export-pdf=$@
|
||||
else ifneq ($(strip $(CONVERT)),)
|
||||
convert $< $@
|
||||
endif
|
||||
|
||||
CorebootPortingGuide.toc: $(FIGS) CorebootBuildingGuide.tex
|
||||
# 2 times to make sure we have a current toc.
|
||||
$(PDFLATEX) CorebootBuildingGuide.tex
|
||||
$(PDFLATEX) CorebootBuildingGuide.tex
|
||||
|
||||
CorebootPortingGuide.pdf: $(FIGS) CorebootBuildingGuide.tex CorebootPortingGuide.toc
|
||||
$(PDFLATEX) CorebootBuildingGuide.tex
|
||||
|
||||
Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
|
||||
$(PDFLATEX) $<
|
||||
|
||||
# quick, somebody! make me a macro!
|
||||
mainboardkconfig.tex: ../src/mainboard/Kconfig
|
||||
cat beginverbatim.tex > $@
|
||||
grep '^config' $< | awk '{print $2}' >>$@
|
||||
cat endverbatim.tex >> $@
|
||||
|
||||
skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
|
||||
cat beginverbatim.tex > $@
|
||||
grep '^config' $< | awk '{print $2}' >>$@
|
||||
cat endverbatim.tex >> $@
|
||||
|
||||
cpukconfig.tex: ../src/cpu/Kconfig
|
||||
cat beginverbatim.tex > $@
|
||||
grep '^config' $< | awk '{print $2}' >>$@
|
||||
cat endverbatim.tex >> $@
|
||||
|
||||
socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
|
||||
cat beginverbatim.tex > $@
|
||||
grep '^config' $< | awk '{print $2}' >>$@
|
||||
cat endverbatim.tex >> $@
|
||||
|
||||
clean:
|
||||
rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex
|
||||
|
||||
distclean: clean
|
||||
rm -f CorebootPortingGuide.pdf Kconfig.pdf
|
||||
|
||||
26
Documentation/POSTCODES
Normal file
26
Documentation/POSTCODES
Normal file
@@ -0,0 +1,26 @@
|
||||
-------------------------------------------------------------------------------
|
||||
coreboot POST Codes
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
This is an (incomplete) list of POST codes emitted by coreboot v4.
|
||||
|
||||
0x10 Entry into protected mode
|
||||
0x01 Entry into 'crt0.s' reset code jumps to here
|
||||
0x11 Start copying coreboot to RAM with decompression if compressed
|
||||
0x12 Copy/decompression finished jumping to RAM
|
||||
0x80 Entry into coreboot in RAM
|
||||
0x13 Entry into c_start
|
||||
0xfe Pre call to hardwaremain()
|
||||
0x39 Console is initialized
|
||||
0x40 Console boot message succeeded
|
||||
0x66 Devices have been enumerated
|
||||
0x88 Devices have been configured
|
||||
0x89 Devices have been enabled
|
||||
0xf8 Entry into elf boot
|
||||
0xf3 Jumping to payload
|
||||
|
||||
Errors (used in several places):
|
||||
|
||||
0xee Not supposed to get here
|
||||
0xff Elfload fail or die() called
|
||||
|
||||
266
Documentation/RFC/chip.tex
Normal file
266
Documentation/RFC/chip.tex
Normal file
@@ -0,0 +1,266 @@
|
||||
RFC for the chip specification architecture
|
||||
|
||||
\begin{abstract}
|
||||
At the end of this document is the original message that motivated the
|
||||
change.
|
||||
\end{abstract}
|
||||
|
||||
\section{Scope}
|
||||
This document defines how LinuxBIOS programmers can specify chips that
|
||||
are used, specified, and initalized. The current scope is for superio
|
||||
chips, but the architecture should allow for specification of other chips such
|
||||
as southbridges. Multiple chips of same or different type are supported.
|
||||
|
||||
\section{Goals}
|
||||
The goals of the new chip architecture are these:
|
||||
\begin{itemize}
|
||||
\item seperate implementation details from specification in the Config file
|
||||
(translation: no more C code in Config files)
|
||||
\item make the specification easier for people to use and understand
|
||||
\item remove private details of a given chip to the chip file as much
|
||||
as possible
|
||||
\item allow unique register-set-specifiers for each chip
|
||||
\end{itemize}
|
||||
|
||||
\section{Specification in the Config file}
|
||||
The specification looks like this:
|
||||
\begin{verbatim}
|
||||
chip <name> [path=<path>] ["<configuration>"]
|
||||
\end{verbatim}
|
||||
The name is in the standard LinuxBIOS form of type/vendor/name, e.g.
|
||||
"southbridge/intel/piix4e" or "superio/ite/it8671f". The class of the
|
||||
chip is derived from the first pathname component of the name, and the chip
|
||||
configuration is derived from the following components.
|
||||
|
||||
The path defines the access mechanism to the chip.
|
||||
It is optional. If present, it overrides the default path to the chip.
|
||||
|
||||
The configuration defines chip-specific configuration details, and is also
|
||||
optional. Note that an empty configuration will leave the chip with
|
||||
no enabled resources. This may be desirable in some cases.
|
||||
|
||||
\section{Results of specifying a chip}
|
||||
|
||||
When one or more chips are specified, the data about the chips
|
||||
is saved until the entire file is parsed. At this point, the config tool
|
||||
creates a file in the build directory called chip.c This file contains
|
||||
a common struct containing information about
|
||||
each individual chip and an array of pointers to these structures.
|
||||
|
||||
For each chip, there are two structures. The structures contain control
|
||||
information for the chip, and register initialization information. The
|
||||
names of the structures are derived by ``flattening'' the chip name,
|
||||
as in the current linuxbios. For example, superio/ite/xyz uses
|
||||
two structs, one called superio_ite_xyz_control and one called
|
||||
superio_ite_xyz_init. The control struct is initialized from the
|
||||
chip name and path information, and has a pointer to the
|
||||
config struct. The config struct is initialized from the quote string
|
||||
|
||||
\begin{verbatim}
|
||||
From rminnich@lanl.gov Fri May 16 10:34:13 2003
|
||||
Date: Tue, 13 May 2003 08:11:46 -0600 (MDT)
|
||||
From: ron minnich <rminnich@lanl.gov>
|
||||
To: linuxbios@clustermatic.org
|
||||
Subject: RFC:new superio proposal
|
||||
|
||||
Abstract:
|
||||
The superio architecture for linuxbios has worked for the last 2
|
||||
years but is being stretched to the limit by the changes in superio chips.
|
||||
The architecture depended on superio resources being relatively constant
|
||||
between chips, but this assumption no longer holds. In this document we
|
||||
propose several alternatives and solicit comments.
|
||||
|
||||
Overview:
|
||||
The superio architecture in linuxbios was developed over time, and
|
||||
modified as circumstances required. In the beginning it was relatively
|
||||
simple and assumed only one superio per mainboard. The latest version
|
||||
allows an arbitrary number of superios per mainboard, and allows complete
|
||||
specification of the superio base I/O address along with the specification
|
||||
of reasonable default valures for both the base I/O address and the
|
||||
superio parameters such as serial enable, baud rate, and so on.
|
||||
|
||||
Specification of superio control parameters is done by a configuration
|
||||
line such as:
|
||||
|
||||
nsuperio sis/950 com1={1} floppy=1 lpt=1
|
||||
|
||||
This fragment sets the superio type to sis/950; sets com1, floppy, and lpt
|
||||
to enabled; and leaves the defaults to com1 (baud rate, etc.) to the
|
||||
default values.
|
||||
|
||||
While it is not obvious, these configuration parameters are fragments of a
|
||||
C initializer. The initializers are used to build a statically initialized
|
||||
structure of this type:
|
||||
|
||||
struct superio {
|
||||
struct superio_control *super; // the ops for the device.
|
||||
unsigned int port; // if non-zero, overrides the default port
|
||||
// com ports. This is not done as an array (yet).
|
||||
// We think it's easier to set up from python if it is not an
|
||||
// array.
|
||||
struct com_ports com1, com2, com3, com4;
|
||||
// DMA, if it exists.
|
||||
struct lpt_ports lpt1, lpt2;
|
||||
/* flags for each device type. Unsigned int. */
|
||||
// low order bit ALWAYS means enable. Next bit means to enable
|
||||
// LPT is in transition, so we leave this here for the moment.
|
||||
// The winbond chips really stretched the way this works.
|
||||
// so many functions!
|
||||
unsigned int ide, floppy, lpt;
|
||||
unsigned int keyboard, cir, game;
|
||||
unsigned int gpio1, gpio2, gpio3;
|
||||
unsigned int acpi,hwmonitor;
|
||||
};
|
||||
|
||||
These structures are, in turn, created and statically initialized by a
|
||||
config-tool-generated structure that defines all the superios. This file
|
||||
is called nsuperio.c, is created for each mainboard you build, only
|
||||
appears in the build directory, and looks like this:
|
||||
|
||||
===
|
||||
extern struct superio_control superio_winbond_w83627hf_control;
|
||||
|
||||
struct superio superio_winbond_w83627hf= {
|
||||
&superio_winbond_w83627hf_control,
|
||||
.com1={1}, .com2={1}, .floppy=1, .lpt=1, .keyboard=1, .hwmonitor=1};
|
||||
|
||||
struct superio *all_superio[] = {&superio_winbond_w83627hf,
|
||||
};
|
||||
|
||||
unsigned long nsuperio = 1;
|
||||
===
|
||||
|
||||
This example shows a board with one superio (nsuperio). The superio
|
||||
consists of a winbond w83627hf, with com1, com2, floppy, lpt, keyboard,
|
||||
and hwmonitor enabled. Note that this structure also allows for
|
||||
over-riding the default superio base, although that capability is rarely
|
||||
used.
|
||||
|
||||
The control structure is used to define how to access the superio for
|
||||
purposes of control. It looks like this:
|
||||
===
|
||||
struct superio_control {
|
||||
void (*pre_pci_init)(struct superio *s);
|
||||
void (*init)(struct superio *s);
|
||||
void (*finishup)(struct superio *s);
|
||||
unsigned int defaultport; /* the defaultport. Can be overridden
|
||||
* by commands in config
|
||||
*/
|
||||
// This is the print name for debugging
|
||||
char *name;
|
||||
};
|
||||
===
|
||||
|
||||
There are three methods for stages of hardwaremain. First is pre_pci_init
|
||||
(for chips like the acer southbridge that require you to enable some
|
||||
resources BEFORE pci scan); init, called during the 'middle' phase of
|
||||
hardwaremain; and finishup, called before the payload is loaded.
|
||||
|
||||
This approach was inspired by and borrows heavily on the Plan 9 kernel
|
||||
configuration tools.
|
||||
|
||||
The problem:
|
||||
|
||||
When the first version of the superio structure came out it was much
|
||||
smaller. It has grown and in the limit this structure is the union of all
|
||||
possibly superio chips. Obviously, in the long term, this is not
|
||||
practical: we can not anticipate all possible superio chips for all time.
|
||||
|
||||
The common PC BIOS solution to this type of problem is to continue with
|
||||
binary structures but add version numbers to them, so that all code that
|
||||
uses a given structure has to check the version number. Personally, I find
|
||||
this grotesque and would rather not work this way.
|
||||
|
||||
Using textual strings for configuration is something I find far more
|
||||
attractive. Plan 9 has shown that this approach has no real limits and
|
||||
suffices for configuration tasks. The Linux kernel does more limited use
|
||||
of strings for configuration, but still depends on them. Strings are
|
||||
easier to read and work with than binary structures, and more important, a
|
||||
lot easier to deal with when things start going wrong.
|
||||
|
||||
The proposed solution:
|
||||
|
||||
What follows are three possible ideas for specifying superio resources and
|
||||
their settings.
|
||||
|
||||
A common part of the new idea is to eliminate the common superio
|
||||
structure, due to the many variations in chips, and make it invisible
|
||||
outside a given superio source file -- the superio structure is now
|
||||
private to a given superio. Thus, sis/950/superio.c would contain its own
|
||||
superio structure definitions, and also might contain more than once
|
||||
instance of these structures (consider a board with 2 sis 950 chips).
|
||||
|
||||
The control structure would change as follows:
|
||||
struct superio_control {
|
||||
int (*create)(struct superio *s);
|
||||
void (*pre_pci_init)(struct superio *s);
|
||||
void (*init)(struct superio *s);
|
||||
void (*finishup)(struct superio *s);
|
||||
unsigned int defaultport; /* the defaultport. Can be overridden
|
||||
* by commands in config
|
||||
*/
|
||||
// This is the print name for debugging
|
||||
char *name;
|
||||
};
|
||||
|
||||
I.e. we add a new function for creating the superio.
|
||||
|
||||
Communication of superio settings from linuxbios to the superio would be
|
||||
via textual strings. The superio structure becomes this:
|
||||
|
||||
struct superio {
|
||||
struct superio_control *super; // the ops for the device.
|
||||
unsigned int port; // if non-zero, overrides the default port
|
||||
struct configuration *config;
|
||||
};
|
||||
|
||||
|
||||
So now the question becomes, what is the configuration structure?
|
||||
There are several choices. The simplest, from my point of view, are
|
||||
keyword-value pairs:
|
||||
struct configuration {
|
||||
const char *keyword;
|
||||
const char *value;
|
||||
};
|
||||
|
||||
These get filled in by the config tool as before. The linuxbios libary can
|
||||
then provide a generic parsing function for the superios to use.
|
||||
|
||||
The remaining question is how should the superio command look in
|
||||
freebios2?
|
||||
|
||||
superio sis/950 "com1=115200,8n1 lpt=1 com2=9600"
|
||||
|
||||
or
|
||||
|
||||
superio sis/950 "com1baud=115200 lpt=1 com1chars=8n1"
|
||||
|
||||
or
|
||||
|
||||
superio sis/950 ((com1 115200 8n1) (lpt 1))
|
||||
|
||||
So, my questions:
|
||||
|
||||
1. Does this new scheme look workable. If not, what needs to change?
|
||||
2. What should the 'struct configuration' be? does keyword/value work?
|
||||
3. what should the superio command look like?
|
||||
|
||||
Comments welcome.
|
||||
|
||||
I'd like to adopt this "RFC" approach for freebios2 as much as we can.
|
||||
There was a lot of give-and-take in the early days of linuxbios about
|
||||
structure and it proved useful. There's a lot that will start happening in
|
||||
freebios2 now, and we need to try to make sure it will work for everyone.
|
||||
|
||||
Those of you who are doing mainboards, please look at freebios2 and see
|
||||
how it looks for you. There's a lot of good work that has been done (not
|
||||
by me so far, thanks Eric and Stefan), and more that needs to be done.
|
||||
Consider trying out romcc as an "assembly code killer". See how it fits
|
||||
together and if you can work with it or need changes. Bring comments back
|
||||
to this list.
|
||||
|
||||
thanks
|
||||
|
||||
ron
|
||||
|
||||
\end{verbatim}
|
||||
291
Documentation/RFC/config.tex
Normal file
291
Documentation/RFC/config.tex
Normal file
@@ -0,0 +1,291 @@
|
||||
New config language for LinuxBIOS
|
||||
|
||||
\begin{abstract}
|
||||
We describe the new configuration language for LinuxBIOS.
|
||||
\end{abstract}
|
||||
|
||||
\section{Scope}
|
||||
This document defines the new configuration language for LinuxBIOS.
|
||||
|
||||
\section{Goals}
|
||||
The goals of the new language are these:
|
||||
\begin{itemize}
|
||||
\item Simplified Makefiles so people can see what is set
|
||||
\item Move from the regular-expression-based language to something
|
||||
a bit more comprehensible and flexible
|
||||
\item make the specification easier for people to use and understand
|
||||
\item allow unique register-set-specifiers for each chip
|
||||
\item allow generic register-set-specifiers for each chip
|
||||
\item generate static initialization code, as needed, for the
|
||||
specifiers.
|
||||
\end{itemize}
|
||||
|
||||
\section{Language}
|
||||
Here is the new language. It is very similar to the old one, differing
|
||||
in only a few respects. It borrows heavily from Greg Watson's suggestions.
|
||||
|
||||
I am presenting it in a pseudo-BNF in the hopes it will be easier. Things
|
||||
in '' are keywords; things in ``'' are strings in the actual text.
|
||||
\begin{verbatim}
|
||||
#exprs are composed of factor or factor + factor etc.
|
||||
expr ::= factor ( ``+'' factor | ``-'' factor | )*
|
||||
#factors are term or term * term or term / term or ...
|
||||
factor ::= term ( ``*'' term | ``/'' term | ... )*
|
||||
#
|
||||
unary-op ::= ``!'' ID
|
||||
# term is a number, hexnumber, ID, unary-op, or a full-blown expression
|
||||
term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)''
|
||||
|
||||
# Option command. Can be an expression or quote-string.
|
||||
# Options are used in the config tool itself (in expressions and 'if')
|
||||
# and are also passed to the C compiler when building linuxbios.
|
||||
# It is an error to have two option commands in a file.
|
||||
# It is an error to have an option command after the ID has been used
|
||||
# in an expression (i.e. 'set after used' is an error)
|
||||
option ::= 'option' ID '=' (``value'' | term)
|
||||
|
||||
# Default command. The ID is set to this value if no option command
|
||||
# is scanned.
|
||||
# Multiple defaults for an ID will produce warning, but not errors.
|
||||
# It is OK to scan a default command after use of an ID.
|
||||
# Options always over-ride defaults.
|
||||
default ::= 'default' ID '=' (``value'' | term)
|
||||
|
||||
# the mainboard, southbridge, northbridge commands
|
||||
# cause sourcing of Config.lb files as in the old config tool
|
||||
# as parts are sourced, a device tree is built. The structure
|
||||
# of the tree is determined by the structure of the components
|
||||
# as they are specified. To attach a superio to a southbridge, for
|
||||
# example, one would do this:
|
||||
# southbridge acer/5432
|
||||
# superio nsc/123
|
||||
# end
|
||||
# end
|
||||
# the tool generates static initializers for this hierarchy.
|
||||
|
||||
# add C code to the current component (motherboard, etc. )
|
||||
# to initialise the component-INDEPENDENT structure members
|
||||
init ::= 'init' ``CODE''
|
||||
|
||||
# add C code to the current component (motherboard, etc. )
|
||||
# to initialise the component-DEPENDENT structure members
|
||||
register ::= 'register' ``CODE''
|
||||
|
||||
|
||||
# mainboard command
|
||||
# statements in this block will set variables controlling the mainboard,
|
||||
# and will also place components (northbridge etc.) in the device tree
|
||||
# under this mainboard
|
||||
mainboard ::= 'mainboard' PATH (statements)* 'end'
|
||||
|
||||
# standard linuxbios commands
|
||||
southbridge ::= 'southbridge' PATH (statemnts)* 'end'
|
||||
northbridge ::= 'northbridge' PATH (statemnts)* 'end'
|
||||
superio ::= 'superio PATH (statemnts)* 'end'
|
||||
cpu ::= 'cpu' PATH (statemnts)* 'end'
|
||||
arch ::= 'arch' PATH (statemnts)* 'end'
|
||||
|
||||
# files for building linuxbios
|
||||
# include a file in crt0.S
|
||||
mainboardinit ::= 'mainboardinit' PATH
|
||||
|
||||
# object file
|
||||
object ::= 'object' PATH
|
||||
# driver objects are just built into the image in a different way
|
||||
driver ::= 'driver' PATH
|
||||
|
||||
# Use the Config.lb file in the PATH
|
||||
dir ::= 'dir' PATH
|
||||
|
||||
# add a file to the set of ldscript files
|
||||
ldscript ::= 'ldscript' PATH
|
||||
|
||||
# dependencies or actions for the makerule command
|
||||
dep ::= 'dep' ``dependency-string''
|
||||
act ::= 'act' ``actions''
|
||||
depsacts ::= (dep | act)*
|
||||
# set up a makerule
|
||||
#
|
||||
makerule ::= 'makerule' PATH depsacts
|
||||
|
||||
#defines for use in makefiles only
|
||||
# note usable in the config tool, not passed to cc
|
||||
makedefine ::= 'makedefine' ``RAWTEXT''
|
||||
|
||||
# add an action to an existing make rule
|
||||
addaction ::= 'addaction' PATH ``ACTION''
|
||||
|
||||
# statements
|
||||
statement ::=
|
||||
option
|
||||
| default
|
||||
| cpu
|
||||
| arch
|
||||
| northbridge
|
||||
| southbridge
|
||||
| superio
|
||||
| object
|
||||
| driver
|
||||
| mainboardinit
|
||||
| makerule
|
||||
| makedefine
|
||||
| addaction
|
||||
| init
|
||||
| register
|
||||
| iif
|
||||
| dir
|
||||
| ldscript
|
||||
|
||||
statements ::= (statement)*
|
||||
|
||||
# target directory specification
|
||||
target ::= 'target' PATH
|
||||
|
||||
# and the whole thing
|
||||
board ::= target (option)* mainboard
|
||||
|
||||
\end{verbatim}
|
||||
|
||||
\subsubsection{Command definitions}
|
||||
\subsubsubsection{option}
|
||||
\subsubsubsection{default}
|
||||
\subsubsubsection{cpu}
|
||||
\subsubsubsection{arch}
|
||||
\subsubsubsection{northbridge}
|
||||
\subsubsubsection{southbridge}
|
||||
\subsubsubsection{superio}
|
||||
\subsubsubsection{object}
|
||||
\subsubsubsection{driver}
|
||||
\subsubsubsection{mainboardinit}
|
||||
\subsubsubsection{makerule}
|
||||
\subsubsubsection{makedefine}
|
||||
\subsubsubsection{addaction}
|
||||
\subsubsubsection{init}
|
||||
\subsubsubsection{register}
|
||||
\subsubsubsection{iif}
|
||||
\subsubsubsection{dir}
|
||||
\subsubsubsection{ldscript}
|
||||
|
||||
|
||||
A sample file:
|
||||
|
||||
\begin{verbatim}
|
||||
target x
|
||||
|
||||
# over-ride the default rom size in the mainboard file
|
||||
option CONFIG_ROM_SIZE=1024*1024
|
||||
mainboard amd/solo
|
||||
end
|
||||
|
||||
\end{verbatim}
|
||||
|
||||
Sample mainboard file
|
||||
\begin{verbatim}
|
||||
#
|
||||
###
|
||||
### Set all of the defaults for an x86 architecture
|
||||
###
|
||||
arch i386 end
|
||||
cpu k8 end
|
||||
#
|
||||
option CONFIG_DEBUG=1
|
||||
default CONFIG_USE_FALLBACK_IMAGE=1
|
||||
option A=(1+2)
|
||||
option B=0xa
|
||||
#
|
||||
###
|
||||
### Build our 16 bit and 32 bit linuxBIOS entry code
|
||||
###
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
mainboardinit cpu/i386/entry32.inc
|
||||
ldscript cpu/i386/entry16.lds
|
||||
ldscript cpu/i386/entry32.lds
|
||||
#
|
||||
###
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if CONFIG_USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript cpu/i386/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript cpu/i386/reset32.lds
|
||||
end
|
||||
.
|
||||
.
|
||||
.
|
||||
if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
|
||||
#
|
||||
###
|
||||
### Romcc output
|
||||
###
|
||||
#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
|
||||
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
|
||||
#mainboardinit ./failover.inc
|
||||
makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
|
||||
makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
|
||||
mainboardinit ./auto.inc
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
northbridge amd/amdk8
|
||||
end
|
||||
southbridge amd/amd8111
|
||||
end
|
||||
#mainboardinit arch/i386/smp/secondary.inc
|
||||
superio nsc/pc87360
|
||||
register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
|
||||
end
|
||||
dir /pc80
|
||||
##dir /src/superio/winbond/w83627hf
|
||||
cpu p5 end
|
||||
cpu p6 end
|
||||
cpu k7 end
|
||||
cpu k8 end
|
||||
#
|
||||
###
|
||||
### Build the objects we have code for in this directory.
|
||||
###
|
||||
##object mainboard.o
|
||||
driver mainboard.o
|
||||
object static_devices.o
|
||||
if CONFIG_HAVE_MP_TABLE object mptable.o end
|
||||
if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
### Location of the DIMM EEPROMS on the SMBUS
|
||||
### This is fixed into a narrow range by the DIMM package standard.
|
||||
###
|
||||
option SMBUS_MEM_DEVICE_START=(0xa << 3)
|
||||
option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
|
||||
option SMBUS_MEM_DEVICE_INC=1
|
||||
#
|
||||
### The linuxBIOS bootloader.
|
||||
###
|
||||
option CONFIG_PAYLOAD_SIZE = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
|
||||
option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
|
||||
#
|
||||
|
||||
\end{verbatim}
|
||||
|
||||
I've found the output of the new tool to be easier to
|
||||
handle. Makefile.settings looks like this, for example:
|
||||
\begin{verbatim}
|
||||
TOP:=/home/rminnich/src/yapps2/freebios2
|
||||
TARGET_DIR:=x
|
||||
export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
|
||||
export CONFIG_ARCH:=i386
|
||||
export CONFIG_RAMBASE:=0x4000
|
||||
export CONFIG_ROM_IMAGE_SIZE:=65535
|
||||
export CONFIG_PAYLOAD_SIZE:=131073
|
||||
export CONFIG_MAX_CPUS:=1
|
||||
export CONFIG_HEAP_SIZE:=8192
|
||||
export CONFIG_STACK_SIZE:=8192
|
||||
export CONFIG_MEMORY_HOLE:=0
|
||||
export COREBOOT_VERSION:=1.1.0
|
||||
export CC:=$(CONFIG_CROSS_COMPILE)gcc
|
||||
|
||||
\end{verbatim}
|
||||
|
||||
In other words, instead of expressions, we see the values. It's easier to
|
||||
deal with.
|
||||
|
||||
22
Documentation/abi-data-consumption.txt
Normal file
22
Documentation/abi-data-consumption.txt
Normal file
@@ -0,0 +1,22 @@
|
||||
This text describes the ABI coreboot presents to downstream users. Such
|
||||
users are payloads and/or operating systems. Therefore, this text serves
|
||||
at what can be relied on for downstream consumption. Anything not explicitly
|
||||
listed as consumable is subject to change without notice.
|
||||
|
||||
Background and Usage
|
||||
|
||||
coreboot passes information to downstream users using coreboot tables. These
|
||||
table definitions can be found in src/include/boot/coreboot_tables.h and
|
||||
payloads/libpayload/include/coreboot_tables.h respectively within coreboot
|
||||
and libpayload. One of the most vital and important pieces of information
|
||||
found within these tables is the memory map of the system indicating
|
||||
available and reserved memory.
|
||||
|
||||
In 2009 cbmem was added to coreboot. The "CBMEM high table memory manager"
|
||||
serves a way for coreboot to bookkeep its own internal data. While some
|
||||
of this data may be exposed through the coreboot tables the data structures
|
||||
used to manage the data within the cbmem area is subject to change.
|
||||
|
||||
Provided the above, if one needs a piece of data exposed to the OS
|
||||
or payload it should reside within the coreboot tables. If it isn't there
|
||||
then a code change will be required to add it to the coreboot tables.
|
||||
1
Documentation/beginverbatim.tex
Normal file
1
Documentation/beginverbatim.tex
Normal file
@@ -0,0 +1 @@
|
||||
\begin{verbatim}
|
||||
421
Documentation/cbfs.txt
Normal file
421
Documentation/cbfs.txt
Normal file
@@ -0,0 +1,421 @@
|
||||
|
||||
Received: from www.crouse-house.com ([199.45.160.146]
|
||||
for coreboot@coreboot.org; Fri, 19 Dec 2008 23:11:59 +0100
|
||||
From: Jordan Crouse <jordan@cosmicpenguin.net>
|
||||
|
||||
|
||||
Greetings. I apologize for the incompleteness of what I am about to
|
||||
discuss. I was planning on working on it leisurely, but my employment
|
||||
circumstances changed and I've been trying to get it completed in a
|
||||
hurry before I had to leave it behind.
|
||||
|
||||
I've been thinking a lot about LAR lately, and ways to make it more
|
||||
extensible and robust. Marc and I have been trading ideas back and
|
||||
forth for a number of months, and over time a clear idea of what I
|
||||
wanted to do started to take shape.
|
||||
|
||||
My goal was to add small things to LAR while retaining the overall
|
||||
scheme. Over time, the scheme evolved slightly, but I think you'll find
|
||||
that it remains true to the original idea. Below is the beginnings of
|
||||
an architecture document - I did it in text form, but if met with
|
||||
aclaim, it should be wikified. This presents what I call CBFS - the
|
||||
next generation LAR for next generation Coreboot. Its easier to
|
||||
describe what it is by describing what changed:
|
||||
|
||||
A header has been added somewhere in the bootblock similar to Carl
|
||||
Daniel's scheme. In addition to the coreboot information, the header
|
||||
reports the size of the ROM, the alignment of the blocks, and the offset
|
||||
of the first component in the CBFS. The master header provides all
|
||||
the information LAR needs plus the magic number information flashrom needs.
|
||||
|
||||
Each "file" (or component, as I style them) now has a type associated
|
||||
with it. The type is used by coreboot to identify the type of file that
|
||||
it is loading, and it can also be used by payloads to group items in the
|
||||
CBFS by type (i.e - bayou can ask for all components that are payloads).
|
||||
|
||||
The header on each "file" (or component, as I like to style them) has
|
||||
been simplified - We now only store the length, the type, the checksum,
|
||||
and the offset to the data. The name scheme remains the same. The
|
||||
addtional information, which is component specific, has been moved to
|
||||
the component itself (see below).
|
||||
|
||||
The components are arranged in the ROM aligned along the specified
|
||||
alignment from the master header - this is to facilitate partial re-write.
|
||||
|
||||
Other then that, the LAR ideas remain pretty much the same.
|
||||
|
||||
The plan for moving the metadata to the components is to allow many
|
||||
different kinds of components, not all of which are groked by coreboot.
|
||||
However, there are three essential component types that are groked by
|
||||
coreboot, and they are defined:
|
||||
|
||||
stage - the stage is being parsed from the original ELF, and stored in
|
||||
the ROM as a single blob of binary data. The load address, start
|
||||
address, compression type and length are stored in the component sub-header.
|
||||
|
||||
payload - this is essentially SELF in different clothing - same idea as
|
||||
SELF, with the sub-header as above.
|
||||
|
||||
optionrom - This is in flux - right now, the optionrom is stored
|
||||
unadulterated and uncompressed, but that is likely to be changed.
|
||||
|
||||
Following this email are two replies containing the v3 code and a new
|
||||
ROM tool to implement this respectively. I told you that I was trying
|
||||
to get this out before I disappear, and I'm not kidding - the code is
|
||||
compile tested and not run-tested. I hope that somebody will embrace
|
||||
this code and take it the rest of the way, otherwise it will die a
|
||||
pretty short death.
|
||||
|
||||
I realize that this will start an awesome flamewar, and I'm looking
|
||||
forward to it. Thanks for listening to me over the years - and good
|
||||
luck with coreboot. When you all make a million dollars, send me a few
|
||||
bucks, will you?
|
||||
|
||||
Jordan
|
||||
|
||||
Coreboot CBFS Specification
|
||||
Jordan Crouse <jordan@cosmicpenguin.net>
|
||||
|
||||
= Introduction =
|
||||
|
||||
This document describes the coreboot CBFS specification (from here
|
||||
referred to as CBFS). CBFS is a scheme for managing independent chunks
|
||||
of data in a system ROM. Though not a true filesystem, the style and
|
||||
concepts are similar.
|
||||
|
||||
|
||||
= Architecture =
|
||||
|
||||
The CBFS architecture looks like the following:
|
||||
|
||||
/---------------\ <-- Start of ROM
|
||||
| /-----------\ | --|
|
||||
| | Header | | |
|
||||
| |-----------| | |
|
||||
| | Name | | |-- Component
|
||||
| |-----------| | |
|
||||
| |Data | | |
|
||||
| |.. | | |
|
||||
| \-----------/ | --|
|
||||
| |
|
||||
| /-----------\ |
|
||||
| | Header | |
|
||||
| |-----------| |
|
||||
| | Name | |
|
||||
| |-----------| |
|
||||
| |Data | |
|
||||
| |.. | |
|
||||
| \-----------/ |
|
||||
| |
|
||||
| ... |
|
||||
| /-----------\ |
|
||||
| | | |
|
||||
| | Bootblock | |
|
||||
| | --------- | |
|
||||
| | Reset | | <- 0xFFFFFFF0
|
||||
| \-----------/ |
|
||||
\---------------/
|
||||
|
||||
|
||||
The CBFS architecture consists of a binary associated with a physical
|
||||
ROM disk referred hereafter as the ROM. A number of independent of
|
||||
components, each with a header prepended on to data are located within
|
||||
the ROM. The components are nominally arranged sequentially, though they
|
||||
are aligned along a pre-defined boundary.
|
||||
|
||||
The bootblock occupies the last 20k of the ROM. Within
|
||||
the bootblock is a master header containing information about the ROM
|
||||
including the size, alignment of the components, and the offset of the
|
||||
start of the first CBFS component within the ROM.
|
||||
|
||||
= Master Header =
|
||||
|
||||
The master header contains essential information about the ROM that is
|
||||
used by both the CBFS implementation within coreboot at runtime as well
|
||||
as host based utilities to create and manage the ROM. The master header
|
||||
will be located somewhere within the bootblock (last 20k of the ROM). A
|
||||
pointer to the location of the header will be located at offset
|
||||
-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a
|
||||
normal x86 system. The pointer will be to physical memory somewhere
|
||||
between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot
|
||||
to locate the header at run time. Build time utilities will
|
||||
need to read the pointer and do the appropriate math to locate the header.
|
||||
|
||||
The following is the structure of the master header:
|
||||
|
||||
struct cbfs_header {
|
||||
u32 magic;
|
||||
u32 version;
|
||||
u32 romsize;
|
||||
u32 bootblocksize;
|
||||
u32 align;
|
||||
u32 offset;
|
||||
u32 architecture;
|
||||
u32 pad[1];
|
||||
} __attribute__((packed));
|
||||
|
||||
The meaning of each member is as follows:
|
||||
|
||||
'magic' is a 32 bit number that identifies the ROM as a CBFS type. The
|
||||
magic
|
||||
number is 0x4F524243, which is 'ORBC' in ASCII.
|
||||
|
||||
'version' is a version number for CBFS header. cbfs_header structure may be
|
||||
different if version is not matched.
|
||||
|
||||
'romsize' is the size of the ROM in bytes. Coreboot will subtract 'size' from
|
||||
0xFFFFFFFF to locate the beginning of the ROM in memory.
|
||||
|
||||
'bootblocksize' is the size of bootblock reserved in firmware image.
|
||||
|
||||
'align' is the number of bytes that each component is aligned to within the
|
||||
ROM. This is used to make sure that each component is aligned correctly
|
||||
with
|
||||
regards to the erase block sizes on the ROM - allowing one to replace a
|
||||
component at runtime without disturbing the others.
|
||||
|
||||
'offset' is the offset of the the first CBFS component (from the start of
|
||||
the ROM). This is to allow for arbitrary space to be left at the beginning
|
||||
of the ROM for things like embedded controller firmware.
|
||||
|
||||
'architecture' describes which architecture (x86, arm, ...) this CBFS is created
|
||||
for.
|
||||
|
||||
= Bootblock =
|
||||
The bootblock is a mandatory component in the ROM. It is located in the
|
||||
last
|
||||
20k of the ROM space, and contains, among other things, the location of the
|
||||
master header and the entry point for the loader firmware. The bootblock
|
||||
does not have a component header attached to it.
|
||||
|
||||
= Components =
|
||||
|
||||
CBFS components are placed in the ROM starting at 'offset' specified in
|
||||
the master header and ending at the bootblock. Thus the total size
|
||||
available
|
||||
for components in the ROM is (ROM size - 20k - 'offset'). Each CBFS
|
||||
component is to be aligned according to the 'align' value in the header.
|
||||
Thus, if a component of size 1052 is located at offset 0 with an 'align'
|
||||
value
|
||||
of 1024, the next component will be located at offset 2048.
|
||||
|
||||
Each CBFS component will be indexed with a unique ASCII string name of
|
||||
unlimited size.
|
||||
|
||||
Each CBFS component starts with a header:
|
||||
|
||||
struct cbfs_file {
|
||||
char magic[8];
|
||||
unsigned int len;
|
||||
unsigned int type;
|
||||
unsigned int checksum;
|
||||
unsigned int offset;
|
||||
};
|
||||
|
||||
'magic' is a magic value used to identify the header. During runtime,
|
||||
coreboot will scan the ROM looking for this value. The default magic is
|
||||
the string 'LARCHIVE'.
|
||||
|
||||
'len' is the length of the data, not including the size of the header and
|
||||
the size of the name.
|
||||
|
||||
'type' is a 32 bit number indicating the type of data that is attached.
|
||||
The data type is used in a number of ways, as detailed in the section
|
||||
below.
|
||||
|
||||
'checksum' is a 32bit checksum of the entire component, including the
|
||||
header and name.
|
||||
|
||||
'offset' is the start of the component data, based off the start of the
|
||||
header.
|
||||
The difference between the size of the header and offset is the size of the
|
||||
component name.
|
||||
|
||||
Immediately following the header will be the name of the component,
|
||||
which will
|
||||
null terminated and 16 byte aligned. The following picture shows the
|
||||
structure of the header:
|
||||
|
||||
/--------\ <- start
|
||||
| Header |
|
||||
|--------| <- sizeof(struct cbfs_file)
|
||||
| Name |
|
||||
|--------| <- 'offset'
|
||||
| Data |
|
||||
| ... |
|
||||
\--------/ <- start + 'offset' + 'len'
|
||||
|
||||
== Searching Alogrithm ==
|
||||
|
||||
To locate a specific component in the ROM, one starts at the 'offset'
|
||||
specified in the CBFS master header. For this example, the offset will
|
||||
be 0.
|
||||
|
||||
From that offset, the code should search for the magic string on the
|
||||
component, jumping 'align' bytes each time. So, assuming that 'align' is
|
||||
16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc.
|
||||
If the offset ever exceeds the allowable range for CBFS components, then no
|
||||
component was found.
|
||||
|
||||
Upon recognizing a component, the software then has to search for the
|
||||
specific name of the component. This is accomplished by comparing the
|
||||
desired name with the string on the component located at
|
||||
offset + sizeof(struct cbfs_file). If the string matches, then the
|
||||
component
|
||||
has been located, otherwise the software should add 'offset' + 'len' to
|
||||
the offset and resume the search for the magic value.
|
||||
|
||||
== Data Types ==
|
||||
|
||||
The 'type' member of struct cbfs_file is used to identify the content
|
||||
of the component data, and is used by coreboot and other
|
||||
run-time entities to make decisions about how to handle the data.
|
||||
|
||||
There are three component types that are essential to coreboot, and so
|
||||
are defined here.
|
||||
|
||||
=== Stages ===
|
||||
|
||||
Stages are code loaded by coreboot during the boot process. They are
|
||||
essential to a successful boot. Stages are comprised of a single blob
|
||||
of binary data that is to be loaded into a particular location in memory
|
||||
and executed. The uncompressed header contains information about how
|
||||
large the data is, and where it should be placed, and what additional memory
|
||||
needs to be cleared.
|
||||
|
||||
Stages are assigned a component value of 0x10. When coreboot sees this
|
||||
component type, it knows that it should pass the data to a sub-function
|
||||
that will process the stage.
|
||||
|
||||
The following is the format of a stage component:
|
||||
|
||||
/--------\
|
||||
| Header |
|
||||
|--------|
|
||||
| Binary |
|
||||
| .. |
|
||||
\--------/
|
||||
|
||||
The header is defined as:
|
||||
|
||||
struct cbfs_stage {
|
||||
unsigned int compression;
|
||||
unsigned long long entry;
|
||||
unsigned long long load;
|
||||
unsigned int len;
|
||||
unsigned int memlen;
|
||||
};
|
||||
|
||||
'compression' is an integer defining how the data is compressed. There
|
||||
are three compression types defined by this version of the standard:
|
||||
none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional
|
||||
types may be added assuming that coreboot understands how to handle the scheme.
|
||||
|
||||
'entry' is a 64 bit value indicating the location where the program
|
||||
counter should jump following the loading of the stage. This should be
|
||||
an absolute physical memory address.
|
||||
|
||||
'load' is a 64 bit value indicating where the subsequent data should be
|
||||
loaded. This should be an absolute physical memory address.
|
||||
|
||||
'len' is the length of the compressed data in the component.
|
||||
|
||||
'memlen' is the amount of memory that will be used by the component when
|
||||
it is loaded.
|
||||
|
||||
The component data will start immediately following the header.
|
||||
|
||||
When coreboot loads a stage, it will first zero the memory from 'load' to
|
||||
'memlen'. It will then decompress the component data according to the
|
||||
specified scheme and place it in memory starting at 'load'. Following that,
|
||||
it will jump execution to the address specified by 'entry'.
|
||||
Some components are designed to execute directly from the ROM - coreboot
|
||||
knows which components must do that and will act accordingly.
|
||||
|
||||
=== Payloads ===
|
||||
|
||||
Payloads are loaded by coreboot following the boot process.
|
||||
|
||||
Stages are assigned a component value of 0x20. When coreboot sees this
|
||||
component type, it knows that it should pass the data to a sub-function
|
||||
that will process the payload. Furthermore, other run time
|
||||
applications such as 'bayou' may easily index all available payloads
|
||||
on the system by searching for the payload type.
|
||||
|
||||
|
||||
The following is the format of a stage component:
|
||||
|
||||
/-----------\
|
||||
| Header |
|
||||
| Segment 1 |
|
||||
| Segment 2 |
|
||||
| ... |
|
||||
|-----------|
|
||||
| Binary |
|
||||
| .. |
|
||||
\-----------/
|
||||
|
||||
The header is as follows:
|
||||
|
||||
struct cbfs_payload {
|
||||
struct cbfs_payload_segment segments;
|
||||
}
|
||||
|
||||
The header contains a number of segments corresponding to the segments
|
||||
that need to be loaded for the payload.
|
||||
|
||||
The following is the structure of each segment header:
|
||||
|
||||
struct cbfs_payload_segment {
|
||||
unsigned int type;
|
||||
unsigned int compression;
|
||||
unsigned int offset;
|
||||
unsigned long long load_addr;
|
||||
unsigned int len;
|
||||
unsigned int mem_len;
|
||||
};
|
||||
|
||||
'type' is the type of segment, one of the following:
|
||||
|
||||
PAYLOAD_SEGMENT_CODE 0x45444F43 The segment contains executable code
|
||||
PAYLOAD_SEGMENT_DATA 0x41544144 The segment contains data
|
||||
PAYLOAD_SEGMENT_BSS 0x20535342 The memory speicfied by the segment
|
||||
should be zeroed
|
||||
PAYLOAD_SEGMENT_PARAMS 0x41524150 The segment contains information for
|
||||
the payload
|
||||
PAYLOAD_SEGMENT_ENTRY 0x52544E45 The segment contains the entry point
|
||||
for the payload
|
||||
|
||||
'compression' is the compression scheme for the segment. Each segment can
|
||||
be independently compressed. There are three compression types defined by
|
||||
this version of the standard: none (0x0), lzma (0x1), and nrv2b
|
||||
(0x02, deprecated), though additional types may be added assuming that
|
||||
coreboot understands how to handle the scheme.
|
||||
|
||||
'offset' is the address of the data within the component, starting from
|
||||
the component header.
|
||||
|
||||
'load_addr' is a 64 bit value indicating where the segment should be placed
|
||||
in memory.
|
||||
|
||||
'len' is a 32 bit value indicating the size of the segment within the
|
||||
component.
|
||||
|
||||
'mem_len' is the size of the data when it is placed into memory.
|
||||
|
||||
The data will located immediately following the last segment.
|
||||
|
||||
=== Option ROMS ===
|
||||
|
||||
The third specified component type will be Option ROMs. Option ROMS will
|
||||
have component type '0x30'. They will have no additional header, the
|
||||
uncompressed binary data will be located in the data portion of the
|
||||
component.
|
||||
|
||||
=== NULL ===
|
||||
|
||||
There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is
|
||||
the "don't care" component type. This can be used when the component
|
||||
type is not necessary (such as when the name of the component is unique.
|
||||
i.e. option_table). It is recommended that all components be assigned a
|
||||
unique type, but NULL can be used when the type does not matter.
|
||||
234
Documentation/codeflow.svg
Normal file
234
Documentation/codeflow.svg
Normal file
@@ -0,0 +1,234 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<svg version="1.1" id="Layer_1" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" x="0px" y="0px"
|
||||
width="256px" height="640px" viewBox="0 0 256 640" enable-background="new 0 0 256 640" xml:space="preserve">
|
||||
<font horiz-adv-x="1000">
|
||||
<font-face font-family="MyriadPro-Regular" units-per-em="1000" underline-position="-100" underline-thickness="50"/>
|
||||
<missing-glyph horiz-adv-x="500" d="M0,0l500,0l0,700l-500,0M250,395l-170,255l340,0M280,350l170,255l0,-510M80,50l170,255l170,-255M50,605l170,-255l-170,-255z"/>
|
||||
<glyph unicode="A" horiz-adv-x="612" d="M424,212l72,-212l93,0l-230,674l-104,0l-230,-674l90,0l70,212M203,280l66,195C283,516 293,558 303,597l2,0C315,558 325,518 340,474l67,-194z"/>
|
||||
<glyph unicode="B" horiz-adv-x="542" d="M76,2C105,-2 151,-6 211,-6C321,-6 397,14 443,57C478,89 501,134 501,192C501,292 426,345 362,360l0,3C432,388 476,445 476,511C476,564 454,604 419,630C378,664 322,679 235,679C175,679 114,673 76,664M163,606C177,609 200,612 240,612C328,612 387,580 387,502C387,437 333,388 242,388l-79,0M163,323l72,0C330,323 409,284 409,193C409,95 326,62 236,62C205,62 181,63 163,66z"/>
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||||
<glyph unicode="C" horiz-adv-x="580" d="M529,91C494,74 440,63 386,63C223,63 128,168 128,334C128,511 233,612 391,612C447,612 494,600 526,584l22,71C525,667 471,685 388,685C179,685 36,543 36,331C36,109 178,-11 368,-11C450,-11 515,5 546,21z"/>
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||||
<glyph unicode="D" horiz-adv-x="666" d="M76,2C120,-3 171,-6 234,-6C365,-6 469,28 533,91C595,153 630,243 630,353C630,462 595,540 534,595C475,649 386,679 261,679C192,679 129,673 76,664M163,601C186,606 220,610 265,610C449,610 539,509 538,350C538,168 438,64 251,64C217,64 185,65 163,68z"/>
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<glyph unicode="E" horiz-adv-x="492" d="M424,388l-261,0l0,213l277,0l0,73l-365,0l0,-674l380,0l0,73l-292,0l0,243l261,0z"/>
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||||
<glyph unicode="F" horiz-adv-x="487" d="M75,0l88,0l0,305l254,0l0,72l-254,0l0,224l275,0l0,73l-363,0z"/>
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<glyph unicode="H" horiz-adv-x="652" d="M75,674l0,-674l88,0l0,316l326,0l0,-316l88,0l0,674l-88,0l0,-282l-326,0l0,282z"/>
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||||
<glyph unicode="I" horiz-adv-x="239" d="M75,674l0,-674l88,0l0,674z"/>
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||||
<glyph unicode="L" horiz-adv-x="472" d="M75,0l376,0l0,73l-288,0l0,601l-88,0z"/>
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||||
<glyph unicode="M" horiz-adv-x="804" d="M660,0l86,0l-42,674l-111,0l-120,-326C443,263 419,189 401,121l-2,0C381,191 359,265 331,348l-115,326l-111,0l-47,-674l83,0l18,289C165,391 170,503 172,587l2,0C193,507 219,421 251,325l110,-321l66,0l119,327C580,424 607,509 631,587l2,0C633,504 639,390 644,296z"/>
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||||
<glyph unicode="N" horiz-adv-x="658" d="M158,0l0,288C158,400 157,481 152,566l3,1C188,494 233,417 280,342l214,-342l88,0l0,674l-82,0l0,-282C500,287 502,205 510,115l-3,-1C476,183 436,254 387,333l-215,341l-96,0l0,-674z"/>
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||||
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||||
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||||
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||||
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||||
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<glyph unicode="T" horiz-adv-x="497" d="M204,0l88,0l0,600l206,0l0,74l-499,0l0,-74l205,0z"/>
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<glyph unicode="," horiz-adv-x="207" d="M78,-117C106,-70 150,41 174,126l-98,-10C65,43 38,-64 16,-124z"/>
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||||
<glyph unicode="d" horiz-adv-x="564" d="M403,710l0,-289l-2,0C379,459 330,494 255,494C138,494 37,396 38,235C38,88 129,-11 246,-11C325,-11 383,30 409,84l3,0l4,-84l78,0C492,33 490,82 490,125l0,585M403,203C403,189 402,177 399,165C383,100 329,60 270,60C176,60 127,141 127,239C127,345 181,425 272,425C338,425 386,379 399,324C402,313 403,298 403,287z"/>
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||||
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|
||||
<glyph unicode="l" horiz-adv-x="236" d="M73,0l88,0l0,710l-88,0z"/>
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After Width: | Height: | Size: 17 KiB |
BIN
Documentation/coreboot_logo.png
Normal file
BIN
Documentation/coreboot_logo.png
Normal file
Binary file not shown.
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After Width: | Height: | Size: 2.2 KiB |
1
Documentation/endverbatim.tex
Normal file
1
Documentation/endverbatim.tex
Normal file
@@ -0,0 +1 @@
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||||
\end{verbatim}
|
||||
227
Documentation/gcov.txt
Normal file
227
Documentation/gcov.txt
Normal file
@@ -0,0 +1,227 @@
|
||||
This patch contains our local modifications for gcov-io.h and libgcov.c.
|
||||
The file gcov-iov.h is taken from a gcc build (produced at compile
|
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time). The file gcov-io.c is unchanged.
|
||||
|
||||
--- gcc-4.7.2/gcc/gcov-io.h 2011-12-04 10:27:19.000000000 -0800
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||||
+++ coreboot/src/lib/gcov-io.h 2013-01-12 16:45:57.000000000 -0800
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||||
@@ -163,6 +163,24 @@
|
||||
#ifndef GCC_GCOV_IO_H
|
||||
#define GCC_GCOV_IO_H
|
||||
|
||||
+#ifdef __COREBOOT__
|
||||
+#define GCOV_LINKAGE /* nothing */
|
||||
+/* We need the definitions for
|
||||
+ BITS_PER_UNIT and
|
||||
+ LONG_LONG_TYPE_SIZE
|
||||
+ They are defined in gcc/defaults.h and gcc/config/<arch_depend_files>
|
||||
+ (like, gcc/config/i386/i386.h). And it can be overridden by setting
|
||||
+ in build scripts. Here I hardcoded the value for x86. */
|
||||
+#define BITS_PER_UNIT 8
|
||||
+#define LONG_LONG_TYPE_SIZE 64
|
||||
+
|
||||
+/* There are many gcc_assertions. Set the vaule to 1 if we want a warning
|
||||
+ message if the assertion fails. */
|
||||
+#ifndef ENABLE_ASSERT_CHECKING
|
||||
+#define ENABLE_ASSERT_CHECKING 1
|
||||
+#endif
|
||||
+#endif /* __COREBOOT__ */
|
||||
+
|
||||
#if IN_LIBGCOV
|
||||
/* About the target */
|
||||
|
||||
@@ -232,7 +250,9 @@
|
||||
is not also used in a DSO. */
|
||||
#if IN_LIBGCOV
|
||||
|
||||
+#ifndef __COREBOOT__
|
||||
#include "tconfig.h"
|
||||
+#endif /* __COREBOOT__ */
|
||||
|
||||
#define gcov_var __gcov_var
|
||||
#define gcov_open __gcov_open
|
||||
@@ -455,8 +475,10 @@
|
||||
/* Register a new object file module. */
|
||||
extern void __gcov_init (struct gcov_info *) ATTRIBUTE_HIDDEN;
|
||||
|
||||
+#ifndef __COREBOOT__
|
||||
/* Called before fork, to avoid double counting. */
|
||||
extern void __gcov_flush (void) ATTRIBUTE_HIDDEN;
|
||||
+#endif
|
||||
|
||||
/* The merge function that just sums the counters. */
|
||||
extern void __gcov_merge_add (gcov_type *, unsigned) ATTRIBUTE_HIDDEN;
|
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--- gcc-4.7.2/libgcc/libgcov.c 2012-01-11 10:50:21.000000000 -0800
|
||||
+++ coreboot/src/lib/libgcov.c 2013-01-16 09:45:11.000000000 -0800
|
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@@ -25,12 +25,41 @@
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
+#define __COREBOOT__
|
||||
+#ifdef __COREBOOT__
|
||||
+#include <stdlib.h>
|
||||
+#include <string.h>
|
||||
+#include <console/console.h>
|
||||
+#include <assert.h>
|
||||
+typedef s32 pid_t;
|
||||
+#define gcc_assert(x) ASSERT(x)
|
||||
+#define fprintf(file, x...) printk(BIOS_ERR, x)
|
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+#define alloca(size) __builtin_alloca (size)
|
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+#include "gcov-glue.c"
|
||||
+
|
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+/* Define MACROs to be used by coreboot compilation. */
|
||||
+# define L_gcov
|
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+# define L_gcov_interval_profiler
|
||||
+# define L_gcov_pow2_profiler
|
||||
+# define L_gcov_one_value_profiler
|
||||
+# define L_gcov_indirect_call_profiler
|
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+# define L_gcov_average_profiler
|
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+# define L_gcov_ior_profiler
|
||||
+
|
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+# define HAVE_CC_TLS 0
|
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+# define __GCOV_KERNEL__
|
||||
+
|
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+# define IN_LIBGCOV 1
|
||||
+# define IN_GCOV 0
|
||||
+#else /* __COREBOOT__ */
|
||||
#include "tconfig.h"
|
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#include "tsystem.h"
|
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#include "coretypes.h"
|
||||
#include "tm.h"
|
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#include "libgcc_tm.h"
|
||||
+#endif /* __COREBOOT__ */
|
||||
|
||||
+#ifndef __COREBOOT__
|
||||
#if defined(inhibit_libc)
|
||||
#define IN_LIBGCOV (-1)
|
||||
#else
|
||||
@@ -41,6 +70,7 @@
|
||||
#define GCOV_LINKAGE /* nothing */
|
||||
#endif
|
||||
#endif
|
||||
+#endif /* __COREBOOT__ */
|
||||
#include "gcov-io.h"
|
||||
|
||||
#if defined(inhibit_libc)
|
||||
@@ -68,12 +98,17 @@
|
||||
|
||||
#else
|
||||
|
||||
+#ifndef __COREBOOT__
|
||||
#include <string.h>
|
||||
#if GCOV_LOCKED
|
||||
#include <fcntl.h>
|
||||
#include <errno.h>
|
||||
#include <sys/stat.h>
|
||||
#endif
|
||||
+#else
|
||||
+void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)),
|
||||
+ unsigned n_counters __attribute__ ((unused))) {}
|
||||
+#endif /* __COREBOOT__ */
|
||||
|
||||
#ifdef L_gcov
|
||||
#include "gcov-io.c"
|
||||
@@ -99,6 +134,10 @@
|
||||
static int
|
||||
create_file_directory (char *filename)
|
||||
{
|
||||
+#ifdef __COREBOOT__
|
||||
+ (void) filename;
|
||||
+ return 0;
|
||||
+#else
|
||||
#if !defined(TARGET_POSIX_IO) && !defined(_WIN32)
|
||||
(void) filename;
|
||||
return -1;
|
||||
@@ -137,6 +176,7 @@
|
||||
};
|
||||
return 0;
|
||||
#endif
|
||||
+#endif
|
||||
}
|
||||
|
||||
static struct gcov_fn_buffer *
|
||||
@@ -279,7 +319,7 @@
|
||||
struct gcov_ctr_summary *cs_ptr;
|
||||
const struct gcov_ctr_info *ci_ptr;
|
||||
unsigned t_ix;
|
||||
- int f_ix;
|
||||
+ int f_ix = 0;
|
||||
gcov_unsigned_t c_num;
|
||||
const char *gcov_prefix;
|
||||
int gcov_prefix_strip = 0;
|
||||
@@ -329,6 +369,7 @@
|
||||
}
|
||||
}
|
||||
|
||||
+#ifndef __COREBOOT__
|
||||
{
|
||||
/* Check if the level of dirs to strip off specified. */
|
||||
char *tmp = getenv("GCOV_PREFIX_STRIP");
|
||||
@@ -352,6 +393,7 @@
|
||||
prefix_length--;
|
||||
}
|
||||
else
|
||||
+#endif
|
||||
prefix_length = 0;
|
||||
|
||||
/* If no prefix was specified and a prefix stip, then we assume
|
||||
@@ -696,8 +738,10 @@
|
||||
if (filename_length > gcov_max_filename)
|
||||
gcov_max_filename = filename_length;
|
||||
|
||||
+#ifndef __COREBOOT__
|
||||
if (!gcov_list)
|
||||
atexit (gcov_exit);
|
||||
+#endif
|
||||
|
||||
info->next = gcov_list;
|
||||
gcov_list = info;
|
||||
@@ -767,14 +811,15 @@
|
||||
|
||||
#ifdef L_gcov_merge_single
|
||||
/* The profile merging function for choosing the most common value.
|
||||
- It is given an array COUNTERS of N_COUNTERS old counters and it
|
||||
- reads the same number of counters from the gcov file. The counters
|
||||
- are split into 3-tuples where the members of the tuple have
|
||||
- meanings:
|
||||
-
|
||||
- -- the stored candidate on the most common value of the measured entity
|
||||
- -- counter
|
||||
- -- total number of evaluations of the value */
|
||||
+ * It is given an array COUNTERS of N_COUNTERS old counters and it
|
||||
+ * reads the same number of counters from the gcov file. The counters
|
||||
+ * are split into 3-tuples where the members of the tuple have
|
||||
+ * meanings:
|
||||
+ *
|
||||
+ * -- the stored candidate on the most common value of the measured entity
|
||||
+ * -- counter
|
||||
+ * -- total number of evaluations of the value
|
||||
+ */
|
||||
void
|
||||
__gcov_merge_single (gcov_type *counters, unsigned n_counters)
|
||||
{
|
||||
@@ -805,15 +850,16 @@
|
||||
|
||||
#ifdef L_gcov_merge_delta
|
||||
/* The profile merging function for choosing the most common
|
||||
- difference between two consecutive evaluations of the value. It is
|
||||
- given an array COUNTERS of N_COUNTERS old counters and it reads the
|
||||
- same number of counters from the gcov file. The counters are split
|
||||
- into 4-tuples where the members of the tuple have meanings:
|
||||
-
|
||||
- -- the last value of the measured entity
|
||||
- -- the stored candidate on the most common difference
|
||||
- -- counter
|
||||
- -- total number of evaluations of the value */
|
||||
+ * difference between two consecutive evaluations of the value. It is
|
||||
+ * given an array COUNTERS of N_COUNTERS old counters and it reads the
|
||||
+ * same number of counters from the gcov file. The counters are split
|
||||
+ * into 4-tuples where the members of the tuple have meanings:
|
||||
+ *
|
||||
+ * -- the last value of the measured entity
|
||||
+ * -- the stored candidate on the most common difference
|
||||
+ * -- counter
|
||||
+ * -- total number of evaluations of the value
|
||||
+ */
|
||||
void
|
||||
__gcov_merge_delta (gcov_type *counters, unsigned n_counters)
|
||||
{
|
||||
59
Documentation/hypertransport.svg
Normal file
59
Documentation/hypertransport.svg
Normal file
@@ -0,0 +1,59 @@
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46
Documentation/submodules.txt
Normal file
46
Documentation/submodules.txt
Normal file
@@ -0,0 +1,46 @@
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||||
Use of git submodules in coreboot
|
||||
=================================
|
||||
coreboot uses git submodules to keep certain parts of the tree separate,
|
||||
with two major use cases:
|
||||
|
||||
First, we use a vendor tool by NVIDIA for systems based on their SoC
|
||||
and since they publish it through git, we can just import it into our
|
||||
tree using submodules.
|
||||
|
||||
Second, lots of boards these days require binaries and we want to keep
|
||||
them separate from coreboot proper to clearly delineate shiny Open Source
|
||||
from ugly blobs.
|
||||
Since we don't want to impose blobs on users who really don't need them,
|
||||
that repository is only downloaded and checked out on explicit request.
|
||||
|
||||
Handling submodules
|
||||
-------------------
|
||||
For the most part, submodules should be automatically checked out on the
|
||||
first execution of the coreboot Makefile.
|
||||
|
||||
To manually fetch all repositories (eg. when you want to prepare the tree
|
||||
for archiving, or to use it without network access), run
|
||||
|
||||
$ git submodule update --init --checkout
|
||||
|
||||
This also checks out the binaries below `3rdparty/`
|
||||
|
||||
Mirroring coreboot
|
||||
------------------
|
||||
When running a coreboot mirror to checkout from, for full operation, you
|
||||
should also mirror the blobs and nvidia-cbootimage repository, and place
|
||||
them in the same directory as the coreboot repository mirror.
|
||||
|
||||
That is, when residing in coreboot's repository, `cd ../blobs.git`
|
||||
should move you to the blobs repository.
|
||||
|
||||
With that, no matter what the URL of your coreboot repository is, the
|
||||
git client (of a sufficiently new version) is able to pick up the other
|
||||
repositories transparently.
|
||||
|
||||
Minimum requirements
|
||||
--------------------
|
||||
git needs to be able to handle relative paths to submodule repositories,
|
||||
and it needs to know about non-automatic submodules.
|
||||
|
||||
For these features, we require git version 1.7.6.1 or newer.
|
||||
Reference in New Issue
Block a user