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aopen/dxplplusu: Add romstage timestamps

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Change-Id: Ic6e2a350a976a3fcb421d47a0bf5600df994edc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2018-06-19 17:09:01 +03:00
parent faad9684a9
commit 4d991550b3
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/aopen/dxplplusu/romstage.c
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@ -22,6 +22,7 @@
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <timestamp.h>
#include <southbridge/intel/i82801dx/i82801dx.h> #include <southbridge/intel/i82801dx/i82801dx.h>
#include <northbridge/intel/e7505/raminit.h> #include <northbridge/intel/e7505/raminit.h>
@ -47,6 +48,9 @@ void mainboard_romstage_entry(unsigned long bist)
}, },
}; };
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* Get the serial port running and print a welcome banner */ /* Get the serial port running and print a welcome banner */
lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
@ -58,6 +62,8 @@ void mainboard_romstage_entry(unsigned long bist)
if (!e7505_mch_is_ready()) { if (!e7505_mch_is_ready()) {
enable_smbus(); enable_smbus();
timestamp_add_now(TS_BEFORE_INITRAM);
/* The real MCH initialisation. */ /* The real MCH initialisation. */
e7505_mch_init(memctrl); e7505_mch_init(memctrl);
@ -75,6 +81,8 @@ void mainboard_romstage_entry(unsigned long bist)
/* Hook for post ECC scrub settings and debug. */ /* Hook for post ECC scrub settings and debug. */
e7505_mch_done(memctrl); e7505_mch_done(memctrl);
timestamp_add_now(TS_AFTER_INITRAM);
} }
printk(BIOS_DEBUG, "SDRAM is up.\n"); printk(BIOS_DEBUG, "SDRAM is up.\n");