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add intel speedstep support and some PM fixes.

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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-07-21 21:41:42 +00:00
committed by Stefan Reinauer
parent b657a3c9b7
commit 4da810bd53
6 changed files with 202 additions and 18 deletions
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8
src/cpu/x86/smm/smmrelocate.S
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@@ -20,7 +20,13 @@
*/
#include <arch/asm.h>
#include "../../../../src/northbridge/intel/i945/ich7.h"
// Make sure no stage 2 code is included:
#define __ROMCC__
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
#undef DEBUG_SMM_RELOCATION
//#define DEBUG_SMM_RELOCATION