mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -10,7 +10,6 @@ config CPU_QEMU_X86
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if CPU_QEMU_X86
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if CPU_QEMU_X86
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# coreboot i440fx does not support SMM
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choice
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choice
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prompt "AP init"
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prompt "AP init"
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default CPU_QEMU_X86_LAPIC_INIT
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default CPU_QEMU_X86_LAPIC_INIT
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@ -24,6 +23,7 @@ config CPU_QEMU_X86_PARALLEL_MP
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endchoice
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endchoice
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# coreboot i440fx does not support SMM
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choice
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choice
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prompt "SMM support"
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prompt "SMM support"
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default CPU_QEMU_X86_ASEG_SMM
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default CPU_QEMU_X86_ASEG_SMM
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@ -35,7 +35,6 @@ config CPU_QEMU_X86_NO_SMM
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config CPU_QEMU_X86_ASEG_SMM
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config CPU_QEMU_X86_ASEG_SMM
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bool "SMM in ASEG"
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bool "SMM in ASEG"
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depends on CPU_QEMU_X86_LAPIC_INIT
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select SMM_ASEG
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select SMM_ASEG
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config CPU_QEMU_X86_TSEG_SMM
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config CPU_QEMU_X86_TSEG_SMM
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@ -36,6 +36,7 @@ struct ied_header {
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/* These helpers are for performing SMM relocation. */
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/* These helpers are for performing SMM relocation. */
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void northbridge_write_smram(u8 smram);
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void northbridge_write_smram(u8 smram);
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void smm_open_aseg(void);
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void smm_lock(void);
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void smm_lock(void);
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void smm_relocate(void);
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void smm_relocate(void);
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@ -247,7 +247,7 @@ extern const struct mp_ops mp_ops_with_smm;
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void mp_init_cpus(struct bus *cpu_bus)
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void mp_init_cpus(struct bus *cpu_bus)
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{
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{
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const struct mp_ops *ops = CONFIG(SMM_TSEG) ? &mp_ops_with_smm : &mp_ops_no_smm;
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const struct mp_ops *ops = CONFIG(NO_SMM) ? &mp_ops_no_smm : &mp_ops_with_smm;
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/* TODO: Handle mp_init_with_smm failure? */
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/* TODO: Handle mp_init_with_smm failure? */
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mp_init_with_smm(cpu_bus, ops);
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mp_init_with_smm(cpu_bus, ops);
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@ -12,7 +12,14 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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{
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{
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
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if (CONFIG(SMM_TSEG))
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
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if (CONFIG(SMM_ASEG)) {
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smm_open_aseg();
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*perm_smbase = 0xa0000;
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*perm_smsize = 0x10000;
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}
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/* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */
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/* FIXME: on X86_64 the save state size is smaller than the size of the SMM stub */
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*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
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*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
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@ -78,6 +78,12 @@ void smm_lock(void)
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*/
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN);
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if (CONFIG(SMM_TSEG))
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pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN);
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pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
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pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
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}
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}
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void smm_open_aseg(void)
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{
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pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, G_SMRAME | C_BASE_SEG | D_OPEN);
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}
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