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Intel cpus: delete dead CAR code and whitespace fixes

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A diff from model_6fx to model_106cx suggests there is little
CORE2 specific code that was once considered useful to have.
In its current status however, sockets supporting model_6fx use
model_6ex CAR init, so that specific code is actually
never used.

Deletes file:
    model_6fx/cache_as_ram.inc

Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/640
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
This commit is contained in:
Kyösti Mälkki
2012-06-28 12:16:12 +03:00
committed by Sven Schnelle
parent aa03af74f1
commit 4dcc5737cd
3 changed files with 3 additions and 299 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/cpu/intel/model_6ex/cache_as_ram.inc
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@@ -83,7 +83,7 @@ clear_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
movl %cr0, %eax
movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -164,18 +164,6 @@ clear_mtrrs:
post_code(0x31)
invd
#if 0
xorl %eax, %eax
xorl %edx, %edx
movl $MTRRphysBase_MSR(0), %ecx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
wrmsr
movl $MTRRphysBase_MSR(1), %ecx
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
wrmsr
#endif
post_code(0x33)
@@ -193,7 +181,7 @@ clear_mtrrs:
post_code(0x38)
/* Enable Write Back and Speculative Reads for the first 1MB. */
/* Enable Write Back and Speculative Reads for low RAM. */
movl $MTRRphysBase_MSR(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx