soc/amd/stoneyridge: Fix most checkpatch errors
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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Martin Roth
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4692e2fc95
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4e101ada37
@@ -53,13 +53,12 @@ static void enable_dev(device_t dev)
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}
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &cpu_bus_ops;
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} else if (dev->path.type == DEVICE_PATH_PCI) {
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else if (dev->path.type == DEVICE_PATH_PCI)
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hudson_enable(dev);
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}
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}
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static void soc_init(void *chip_info)
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