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src: Fix MSR_PKG_CST_CONFIG_CONTROL register name

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Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Elyes HAOUAS
2018-10-02 08:44:47 +02:00
committed by Martin Roth
parent 19c0ae540e
commit 4e6b7907de
25 changed files with 38 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/fsp_model_206ax/finalize.c
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@@ -45,7 +45,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
void intel_model_206ax_finalize_smm(void)
{
/* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))

2
src/cpu/intel/fsp_model_206ax/model_206ax.h
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@@ -43,7 +43,7 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_MISC_PWR_MGMT 0x1aa

2
src/cpu/intel/fsp_model_406dx/model_406dx.h
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@@ -45,7 +45,7 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_MISC_PWR_MGMT 0x1aa

2
src/cpu/intel/haswell/finalize.c
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@@ -48,7 +48,7 @@ void intel_cpu_haswell_finalize_smm(void)
{
#if 0
/* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))

2
src/cpu/intel/haswell/haswell.h
View File

@@ -58,7 +58,7 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
#define MSR_PMG_IO_CAPTURE_BASE 0xe4
#define MSR_MISC_PWR_MGMT 0x1aa

4
src/cpu/intel/haswell/haswell_init.c
View File

@@ -486,7 +486,7 @@ static void configure_c_states(void)
{
msr_t msr;
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 30); // Package c-state Undemotion Enable
msr.lo |= (1 << 29); // Package c-state Demotion Enable
msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
@@ -495,7 +495,7 @@ static void configure_c_states(void)
msr.lo |= (1 << 25); // C3 Auto Demotion Enable
msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
/* The deepest package c-state defaults to factory-configured value. */
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
msr.lo &= ~0xffff;

8
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@@ -63,7 +63,7 @@ static void configure_c_states(const int quad)
const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo |= (1 << 8);
if (quad)
@@ -79,7 +79,7 @@ static void configure_c_states(const int quad)
msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */
if (c6)
msr.lo |= (1 << 25);
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE */
msr.hi = 0;
@@ -129,10 +129,10 @@ static void configure_p_states(const char stepping, const char cores)
wrmsr(IA32_PERF_CTL, msr);
}
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo &= ~(1 << 11); /* Enable hw coordination. */
msr.lo |= (1 << 15); /* Lock config until next reset. */
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
}
#define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x))

4
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@@ -32,14 +32,14 @@ static void configure_c_states(void)
{
msr_t msr;
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // Lock configuration
msr.lo |= (1 << 10); // redirect IO-based CState transition requests to
// MWAIT
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;

2
src/cpu/intel/model_2065x/finalize.c
View File

@@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
void intel_model_2065x_finalize_smm(void)
{
/* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))

2
src/cpu/intel/model_206ax/finalize.c
View File

@@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
void intel_model_206ax_finalize_smm(void)
{
/* Lock C-State MSR */
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))

4
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@@ -252,14 +252,14 @@ static void configure_c_states(void)
{
msr_t msr;
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
msr.lo |= (1 << 27); // C3 Auto Undemotion Enable
msr.lo |= (1 << 26); // C1 Auto Demotion Enable
msr.lo |= (1 << 25); // C3 Auto Demotion Enable
msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
msr.lo |= 7; // No package C-state limit
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);
msr.lo &= ~0x7ffff;

4
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@@ -33,7 +33,7 @@ static void configure_c_states(void)
{
msr_t msr;
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // config lock until next reset
msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
@@ -43,7 +43,7 @@ static void configure_c_states(void)
msr.lo &= ~7;
msr.lo |= HIGHEST_CLEVEL; // support at most C3
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;

4
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@@ -33,7 +33,7 @@ static void configure_c_states(void)
{
msr_t msr;
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
msr.lo |= (1 << 15); // config lock until next reset
msr.lo |= (1 << 14); // Deeper Sleep
msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
@@ -44,7 +44,7 @@ static void configure_c_states(void)
msr.lo &= ~7;
msr.lo |= HIGHEST_CLEVEL; // support at most C3
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* Set Processor MWAIT IO BASE (P_BLK) */
msr.hi = 0;