src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
committed by
Martin Roth
parent
19c0ae540e
commit
4e6b7907de
@ -45,7 +45,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
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void intel_model_206ax_finalize_smm(void)
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{
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/* Lock C-State MSR */
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msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
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msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
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/* Lock AES-NI only if supported */
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if (cpuid_ecx(1) & (1 << 25))
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@ -43,7 +43,7 @@
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PMG_IO_CAPTURE_BASE 0xe4
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#define MSR_MISC_PWR_MGMT 0x1aa
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@ -45,7 +45,7 @@
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PMG_IO_CAPTURE_BASE 0xe4
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#define MSR_MISC_PWR_MGMT 0x1aa
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@ -48,7 +48,7 @@ void intel_cpu_haswell_finalize_smm(void)
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{
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#if 0
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/* Lock C-State MSR */
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msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
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msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
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/* Lock AES-NI only if supported */
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if (cpuid_ecx(1) & (1 << 25))
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@ -58,7 +58,7 @@
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
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#define MSR_PMG_IO_CAPTURE_BASE 0xe4
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#define MSR_MISC_PWR_MGMT 0x1aa
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@ -486,7 +486,7 @@ static void configure_c_states(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 30); // Package c-state Undemotion Enable
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msr.lo |= (1 << 29); // Package c-state Demotion Enable
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msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
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@ -495,7 +495,7 @@ static void configure_c_states(void)
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msr.lo |= (1 << 25); // C3 Auto Demotion Enable
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msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
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/* The deepest package c-state defaults to factory-configured value. */
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
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msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
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msr.lo &= ~0xffff;
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@ -63,7 +63,7 @@ static void configure_c_states(const int quad)
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const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
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msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
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msr.lo |= (1 << 8);
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if (quad)
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@ -79,7 +79,7 @@ static void configure_c_states(const int quad)
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msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */
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if (c6)
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msr.lo |= (1 << 25);
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
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/* Set Processor MWAIT IO BASE */
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msr.hi = 0;
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@ -129,10 +129,10 @@ static void configure_p_states(const char stepping, const char cores)
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wrmsr(IA32_PERF_CTL, msr);
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}
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
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msr.lo &= ~(1 << 11); /* Enable hw coordination. */
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msr.lo |= (1 << 15); /* Lock config until next reset. */
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
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}
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#define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x))
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@ -32,14 +32,14 @@ static void configure_c_states(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 15); // Lock configuration
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msr.lo |= (1 << 10); // redirect IO-based CState transition requests to
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// MWAIT
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msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
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msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
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// TODO Do we want Deep C4 and Dynamic L2 shrinking?
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
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/* Set Processor MWAIT IO BASE (P_BLK) */
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msr.hi = 0;
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@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
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void intel_model_2065x_finalize_smm(void)
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{
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/* Lock C-State MSR */
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msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
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msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
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/* Lock AES-NI only if supported */
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if (cpuid_ecx(1) & (1 << 25))
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@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
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void intel_model_206ax_finalize_smm(void)
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{
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/* Lock C-State MSR */
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msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
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msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
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/* Lock AES-NI only if supported */
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if (cpuid_ecx(1) & (1 << 25))
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@ -252,14 +252,14 @@ static void configure_c_states(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
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msr.lo |= (1 << 27); // C3 Auto Undemotion Enable
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msr.lo |= (1 << 26); // C1 Auto Demotion Enable
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msr.lo |= (1 << 25); // C3 Auto Demotion Enable
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msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
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msr.lo |= 7; // No package C-state limit
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
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msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);
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msr.lo &= ~0x7ffff;
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@ -33,7 +33,7 @@ static void configure_c_states(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 15); // config lock until next reset
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msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
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msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
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@ -43,7 +43,7 @@ static void configure_c_states(void)
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msr.lo &= ~7;
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msr.lo |= HIGHEST_CLEVEL; // support at most C3
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
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/* Set Processor MWAIT IO BASE (P_BLK) */
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msr.hi = 0;
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@ -33,7 +33,7 @@ static void configure_c_states(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
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msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
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msr.lo |= (1 << 15); // config lock until next reset
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msr.lo |= (1 << 14); // Deeper Sleep
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msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
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@ -44,7 +44,7 @@ static void configure_c_states(void)
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msr.lo &= ~7;
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msr.lo |= HIGHEST_CLEVEL; // support at most C3
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wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
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wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
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/* Set Processor MWAIT IO BASE (P_BLK) */
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msr.hi = 0;
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