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src: Fix MSR_PKG_CST_CONFIG_CONTROL register name

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Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This commit is contained in:
Elyes HAOUAS
2018-10-02 08:44:47 +02:00
committed by Martin Roth
parent 19c0ae540e
commit 4e6b7907de
25 changed files with 38 additions and 38 deletions
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2
src/soc/intel/baytrail/cpu.c
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@@ -35,7 +35,7 @@
/* Core level MSRs */
const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_POWER_MISC,
~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
/* Disable C1E */