src: Fix MSR_PKG_CST_CONFIG_CONTROL register name

Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>

src/cpu/intel/fsp_model_206ax/finalize.c

@@ -45,7 +45,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
 void intel_model_206ax_finalize_smm(void)
 {
 	/* Lock C-State MSR */
-	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+	msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
 	if (cpuid_ecx(1) & (1 << 25))

src/cpu/intel/fsp_model_206ax/model_206ax.h

@@ -43,7 +43,7 @@
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce
 #define  PLATFORM_INFO_SET_TDP		(1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define MSR_PMG_IO_CAPTURE_BASE		0xe4
 
 #define MSR_MISC_PWR_MGMT		0x1aa

src/cpu/intel/fsp_model_406dx/model_406dx.h

@@ -45,7 +45,7 @@
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce
 #define  PLATFORM_INFO_SET_TDP		(1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define MSR_PMG_IO_CAPTURE_BASE		0xe4
 
 #define MSR_MISC_PWR_MGMT		0x1aa

src/cpu/intel/haswell/finalize.c

@@ -48,7 +48,7 @@ void intel_cpu_haswell_finalize_smm(void)
 {
 #if 0
 	/* Lock C-State MSR */
-	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+	msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
 	if (cpuid_ecx(1) & (1 << 25))

src/cpu/intel/haswell/haswell.h

@@ -58,7 +58,7 @@
 #define MSR_PIC_MSG_CONTROL		0x2e
 #define MSR_PLATFORM_INFO		0xce
 #define  PLATFORM_INFO_SET_TDP		(1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define MSR_PMG_IO_CAPTURE_BASE		0xe4
 
 #define MSR_MISC_PWR_MGMT		0x1aa

src/cpu/intel/haswell/haswell_init.c

@@ -486,7 +486,7 @@ static void configure_c_states(void)
 {
 	msr_t msr;
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo |= (1 << 30);	// Package c-state Undemotion Enable
 	msr.lo |= (1 << 29);	// Package c-state Demotion Enable
 	msr.lo |= (1 << 28);	// C1 Auto Undemotion Enable
@@ -495,7 +495,7 @@ static void configure_c_states(void)
 	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
 	msr.lo &= ~(1 << 10);	// Disable IO MWAIT redirection
 	/* The deepest package c-state defaults to factory-configured value. */
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
 	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
 	msr.lo &= ~0xffff;

src/cpu/intel/model_1067x/model_1067x_init.c

@@ -63,7 +63,7 @@ static void configure_c_states(const int quad)
 
 	const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo &= ~(1 << 9); // Issue a  single stop grant cycle upon stpclk
 	msr.lo |=  (1 << 8);
 	if (quad)
@@ -79,7 +79,7 @@ static void configure_c_states(const int quad)
 	msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */
 	if (c6)
 		msr.lo |= (1 << 25);
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
 	/* Set Processor MWAIT IO BASE */
 	msr.hi = 0;
@@ -129,10 +129,10 @@ static void configure_p_states(const char stepping, const char cores)
 		wrmsr(IA32_PERF_CTL, msr);
 	}
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo &= ~(1 << 11); /* Enable hw coordination. */
 	msr.lo |= (1 << 15); /* Lock config until next reset. */
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 }
 
 #define MSR_EMTTM_CR_TABLE(x)	(0xa8 + (x))

src/cpu/intel/model_106cx/model_106cx_init.c

@@ -32,14 +32,14 @@ static void configure_c_states(void)
 {
 	msr_t msr;
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo |= (1 << 15); // Lock configuration
 	msr.lo |= (1 << 10); // redirect IO-based CState transition requests to
 			     // MWAIT
 	msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
 	msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
 	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
 	/* Set Processor MWAIT IO BASE (P_BLK) */
 	msr.hi = 0;

src/cpu/intel/model_2065x/finalize.c

@@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
 void intel_model_2065x_finalize_smm(void)
 {
 	/* Lock C-State MSR */
-	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+	msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
 	if (cpuid_ecx(1) & (1 << 25))

src/cpu/intel/model_206ax/finalize.c

@@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit)
 void intel_model_206ax_finalize_smm(void)
 {
 	/* Lock C-State MSR */
-	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+	msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
 
 	/* Lock AES-NI only if supported */
 	if (cpuid_ecx(1) & (1 << 25))

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -252,14 +252,14 @@ static void configure_c_states(void)
 {
 	msr_t msr;
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo |= (1 << 28);	// C1 Auto Undemotion Enable
 	msr.lo |= (1 << 27);	// C3 Auto Undemotion Enable
 	msr.lo |= (1 << 26);	// C1 Auto Demotion Enable
 	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
 	msr.lo &= ~(1 << 10);	// Disable IO MWAIT redirection
 	msr.lo |= 7;		// No package C-state limit
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
 	msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR);
 	msr.lo &= ~0x7ffff;

src/cpu/intel/model_6ex/model_6ex_init.c

@@ -33,7 +33,7 @@ static void configure_c_states(void)
 {
 	msr_t msr;
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo |= (1 << 15); // config lock until next reset
 	msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
 	msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
@@ -43,7 +43,7 @@ static void configure_c_states(void)
 	msr.lo &= ~7;
 	msr.lo |= HIGHEST_CLEVEL; // support at most C3
 
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
 	/* Set Processor MWAIT IO BASE (P_BLK) */
 	msr.hi = 0;

src/cpu/intel/model_6fx/model_6fx_init.c

@@ -33,7 +33,7 @@ static void configure_c_states(void)
 {
 	msr_t msr;
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo |= (1 << 15); // config lock until next reset
 	msr.lo |= (1 << 14); // Deeper Sleep
 	msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
@@ -44,7 +44,7 @@ static void configure_c_states(void)
 	msr.lo &= ~7;
 	msr.lo |= HIGHEST_CLEVEL; // support at most C3
 
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
 	/* Set Processor MWAIT IO BASE (P_BLK) */
 	msr.hi = 0;

src/include/cpu/intel/speedstep.h

@@ -43,7 +43,7 @@
 #define MSR_EBC_FREQUENCY_ID	0x2c
 #define MSR_FSB_FREQ		0xcd
 #define MSR_FSB_CLOCK_VCC	0xce
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define MSR_PMG_IO_BASE_ADDR	0xe3
 #define MSR_PMG_IO_CAPTURE_ADDR	0xe4
 #define MSR_EXTENDED_CONFIG	0xee

src/soc/intel/apollolake/cpu.c

@@ -47,7 +47,7 @@
 static const struct reg_script core_msr_script[] = {
 #if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
 	/* Enable C-state and IO/MWAIT redirect */
-	REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL,
+	REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL,
 		(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
 		| IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)),
 	/* Power Management I/O base address for I/O trapping to C-states */

src/soc/intel/baytrail/cpu.c

@@ -35,7 +35,7 @@
 /* Core level MSRs */
 const struct reg_script core_msr_script[] = {
 	/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
-	REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
+	REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
 	REG_MSR_RMW(MSR_POWER_MISC,
 		    ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
 	/* Disable C1E */

src/soc/intel/baytrail/include/soc/msr.h

@@ -19,7 +19,7 @@
 #define MSR_IA32_PLATFORM_ID		0x17
 #define MSR_BSEL_CR_OVERCLOCK_CONTROL	0xcd
 #define MSR_PLATFORM_INFO		0xce
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define	SINGLE_PCTL			(1 << 11)
 #define MSR_POWER_MISC			0x120
 #define	ENABLE_ULFM_AUTOCM_MASK		(1 << 2)

src/soc/intel/braswell/cpu.c

@@ -36,7 +36,7 @@
 /* Core level MSRs */
 static const struct reg_script core_msr_script[] = {
 	/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
-	REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
+	REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
 	REG_MSR_RMW(MSR_POWER_MISC,
 		    ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
 	/* Disable C1E */

src/soc/intel/braswell/include/soc/msr.h

@@ -21,7 +21,7 @@
 #define MSR_IA32_BIOS_SIGN_ID		0x8B
 #define MSR_BSEL_CR_OVERCLOCK_CONTROL	0xcd
 #define MSR_PLATFORM_INFO		0xce
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define		SINGLE_PCTL			(1 << 11)
 #define MSR_POWER_MISC			0x120
 #define		ENABLE_ULFM_AUTOCM_MASK		(1 << 2)

src/soc/intel/broadwell/cpu.c

@@ -394,7 +394,7 @@ static void configure_c_states(void)
 {
 	msr_t msr;
 
-	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
 	msr.lo |= (1 << 31);	// Timed MWAIT Enable
 	msr.lo |= (1 << 30);	// Package c-state Undemotion Enable
 	msr.lo |= (1 << 29);	// Package c-state Demotion Enable
@@ -404,7 +404,7 @@ static void configure_c_states(void)
 	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
 	msr.lo &= ~(1 << 10);	// Disable IO MWAIT redirection
 	/* The deepest package c-state defaults to factory-configured value. */
-	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+	wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
 
 	msr = rdmsr(MSR_MISC_PWR_MGMT);
 	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination

src/soc/intel/broadwell/include/soc/msr.h

@@ -23,7 +23,7 @@
 #define  CPUID_SMX			(1 << 6)
 #define MSR_PLATFORM_INFO		0xce
 #define  PLATFORM_INFO_SET_TDP		(1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define MSR_PMG_IO_CAPTURE_BASE		0xe4
 #define MSR_FEATURE_CONFIG		0x13c
 #define SMM_MCA_CAP_MSR			0x17d

src/soc/intel/common/block/include/intelblocks/msr.h

@@ -25,14 +25,14 @@
 #define  SGX_GLOBAL_ENABLE	(1 << 18)
 #define  PLATFORM_INFO_SET_TDP	(1 << 29)
 #define MSR_PLATFORM_INFO	0xce
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
-/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
+/* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
 #define   PKG_C_STATE_LIMIT_C2_MASK	0x2
-/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
+/* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
 #define   CORE_C_STATE_LIMIT_C10_MASK	0x70
-/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
+/* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
 #define   IO_MWAIT_REDIRECT_MASK	0x400
-/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
+/* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
 #define   CST_CFG_LOCK_MASK	0x8000
 #define MSR_BIOS_UPGD_TRIG	0x7a
 #define  SGX_ACTIVATE_BIT	(1)

src/soc/intel/denverton_ns/include/soc/msr.h

@@ -26,7 +26,7 @@
 #define CPUID_SMX (1 << 6)
 #define MSR_PLATFORM_INFO 0xce
 #define PLATFORM_INFO_SET_TDP (1 << 29)
-#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL 0xe2
 #define MSR_PMG_IO_CAPTURE_BASE 0xe4
 #define MSR_FEATURE_CONFIG 0x13c
 #define SMM_MCA_CAP_MSR 0x17d

src/soc/intel/fsp_baytrail/cpu.c

@@ -35,7 +35,7 @@
 /* Core level MSRs */
 static const struct reg_script core_msr_script[] = {
 	/* Dynamic L2 shrink enable and threshold */
-	REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
+	REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
 	/* Disable C1E */
 	REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
 	REG_MSR_OR(MSR_POWER_MISC, 0x44),

src/soc/intel/fsp_baytrail/include/soc/msr.h

@@ -19,7 +19,7 @@
 #define MSR_IA32_PLATFORM_ID		0x17
 #define MSR_BSEL_CR_OVERCLOCK_CONTROL	0xcd
 #define MSR_PLATFORM_INFO		0xce
-#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PKG_CST_CONFIG_CONTROL	0xe2
 #define MSR_POWER_MISC			0x120
 #define MSR_IA32_PERF_CTL		0x199
 #define MSR_IA32_MISC_ENABLES		0x1a0