Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@@ -85,7 +85,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -3,7 +3,7 @@ if BOARD_EMULATION_QEMU_X86_I440FX
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_QEMU_X86
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select NO_MMCONF_SUPPORT
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select NO_ECAM_MMCONF_SUPPORT
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select SOUTHBRIDGE_INTEL_I82371EB
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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@@ -56,10 +56,10 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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default "QEMU x86 q35/ich9"
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config MMCONF_BASE_ADDRESS
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config ECAM_MMCONF_BASE_ADDRESS
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default 0xb0000000
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config MMCONF_BUS_NUMBER
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config ECAM_MMCONF_BUS_NUMBER
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int
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default 256
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@@ -11,12 +11,12 @@ static void bootblock_northbridge_init(void)
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{
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/*
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
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* setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
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* to true. That way all subsequent non-explicit config accesses use
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
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* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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@@ -14,7 +14,7 @@
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static uint32_t encode_pciexbar_length(void)
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{
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switch (CONFIG_MMCONF_BUS_NUMBER) {
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switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
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case 256: return 0 << 1;
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case 128: return 1 << 1;
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case 64: return 2 << 1;
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@@ -24,7 +24,7 @@ static uint32_t encode_pciexbar_length(void)
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uint32_t make_pciexbar(void)
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{
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return CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
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return CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
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}
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/* Check that MCFG is active. If it's not, QEMU was started for machine PC */
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@@ -79,7 +79,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -88,7 +88,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -57,7 +57,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -94,7 +94,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -17,7 +17,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -54,7 +54,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -59,7 +59,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -15,7 +15,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -13,7 +13,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -43,7 +43,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -119,7 +119,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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@@ -104,7 +104,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
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.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
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.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
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.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
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.wdbbar = 0x4000000,
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.wdbsize = 0x1000,
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