sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Rename ECAM-specific MMCONF Kconfigs

Browse Source 
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Shelley Chen
2021-10-20 15:43:45 -07:00
parent 5c163bb869
commit 4e9bb3308e
104 changed files with 205 additions and 194 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/amd/agesa/family14/Kconfig
View File

@@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY14

4
src/northbridge/amd/agesa/family15tn/Kconfig
View File

@@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN

4
src/northbridge/amd/agesa/family16kb/Kconfig
View File

@@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID

4
src/northbridge/amd/pi/00730F01/Kconfig
View File

@@ -10,10 +10,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID

2
src/northbridge/intel/e7505/Kconfig
View File

@@ -7,7 +7,7 @@ if NORTHBRIDGE_INTEL_E7505
config NORTHBRIDGE_SPECIFIC_OPTIONS
def_bool y
select NO_MMCONF_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE
select LEGACY_SMP_INIT

4
src/northbridge/intel/gm45/Kconfig
View File

@@ -23,10 +23,10 @@ config VGA_BIOS_ID
string
default "8086,2a42"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

2
src/northbridge/intel/gm45/acpi/gm45.asl
View File

@@ -16,7 +16,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

8
src/northbridge/intel/gm45/bootblock.c
View File

@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -21,17 +21,17 @@ void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
* true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
}

4
src/northbridge/intel/haswell/Kconfig
View File

@@ -32,10 +32,10 @@ config VGA_BIOS_ID
string
default "8086,0166"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

6
src/northbridge/intel/haswell/acpi/hostbridge.asl
View File

@@ -125,7 +125,7 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
// PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -161,7 +161,7 @@ Method (_CRS, 0, Serialized)
}
PMIN = Local0
PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
PLEN = (PMAX - PMIN) + 1
Return (MCRS)
@@ -178,7 +178,7 @@ Device (PDRC)
Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

8
src/northbridge/intel/haswell/bootblock.c
View File

@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -21,15 +21,15 @@ void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

2
src/northbridge/intel/haswell/haswell_mrc/raminit.c
View File

@@ -349,7 +349,7 @@ void perform_raminit(const int s3resume)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = CONFIG_FIXED_RCBA_MMIO_BASE,

2
src/northbridge/intel/i440bx/Kconfig
View File

@@ -2,7 +2,7 @@
config NORTHBRIDGE_INTEL_I440BX
bool
select NO_MMCONF_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE
select LEGACY_SMP_INIT

4
src/northbridge/intel/i945/Kconfig
View File

@@ -35,10 +35,10 @@ config I945_LVDS
for the LVDS port. A linear framebuffer is only supported for
LVDS.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

2
src/northbridge/intel/i945/acpi/i945.asl
View File

@@ -40,7 +40,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

16
src/northbridge/intel/i945/bootblock.c
View File

@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -20,14 +20,16 @@ static uint32_t encode_pciexbar_length(void)
void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
* because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
* config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final assumption is that
* no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way
* all subsequent non-explicit config accesses use MCFG. This code also
* assumes that bootblock_northbridge_init() is the first thing called
* in the non-asm boot block code. The final assumption is that no
* assembly code is using the CONFIG(ECAM_MMCONF_SUPPORT) option to do
* PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

4
src/northbridge/intel/ironlake/Kconfig
View File

@@ -39,10 +39,10 @@ config DCACHE_BSP_STACK_SIZE
The amount of anticipated stack usage in CAR by bootblock and
other stages.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 256
config INTEL_GMA_BCLV_OFFSET

2
src/northbridge/intel/ironlake/acpi/ironlake.asl
View File

@@ -14,7 +14,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

4
src/northbridge/intel/ironlake/bootblock.c
View File

@@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
/* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 6 << 1;
case 64: return 7 << 1;
@@ -27,7 +27,7 @@ void bootblock_early_northbridge_init(void)
*/
const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0);
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32);
}

2
src/northbridge/intel/ironlake/ironlake.h
View File

@@ -21,7 +21,7 @@
#include "memmap.h"
#define QUICKPATH_BUS (CONFIG_MMCONF_BUS_NUMBER - 1)
#define QUICKPATH_BUS (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1)
#include <southbridge/intel/ibexpeak/pch.h>

4
src/northbridge/intel/pineview/Kconfig
View File

@@ -19,10 +19,10 @@ config VGA_BIOS_ID
string
default "8086,a001"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

2
src/northbridge/intel/pineview/acpi/pineview.asl
View File

@@ -15,7 +15,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */

4
src/northbridge/intel/pineview/bootblock.c
View File

@@ -8,7 +8,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -18,6 +18,6 @@ static uint32_t encode_pciexbar_length(void)
void bootblock_early_northbridge_init(void)
{
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

4
src/northbridge/intel/sandybridge/Kconfig
View File

@@ -83,12 +83,12 @@ config VGA_BIOS_ID
string
default "8086,0106"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
help
The MRC blob requires it to be at 0xf0000000.
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

4
src/northbridge/intel/sandybridge/acpi/hostbridge.asl
View File

@@ -320,7 +320,7 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
// PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -356,7 +356,7 @@ Method (_CRS, 0, Serialized)
}
PMIN = Local0
PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
PLEN = PMAX - PMIN + 1
Return (MCRS)

8
src/northbridge/intel/sandybridge/bootblock.c
View File

@@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -21,15 +21,15 @@ void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

2
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@@ -231,7 +231,7 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data)
pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE;
pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE;
pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE;
pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
pei_data->hpet_address = CONFIG_HPET_ADDRESS;
pei_data->thermalbase = 0xfed08000;
pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE);

4
src/northbridge/intel/x4x/Kconfig
View File

@@ -21,10 +21,10 @@ config VGA_BIOS_ID
string
default "8086,2e32"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

2
src/northbridge/intel/x4x/acpi/x4x.asl
View File

@@ -13,7 +13,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

4
src/northbridge/intel/x4x/bootblock.c
View File

@@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -23,6 +23,6 @@ void bootblock_early_northbridge_init(void)
/* Disable LaGrande Technology (LT) */
read32((void *)TPM_BASE_ADDRESS);
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
}