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Rename ECAM-specific MMCONF Kconfigs

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Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Shelley Chen
2021-10-20 15:43:45 -07:00
parent 5c163bb869
commit 4e9bb3308e
104 changed files with 205 additions and 194 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/northbridge/intel/x4x/bootblock.c
View File

@@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@@ -23,6 +23,6 @@ void bootblock_early_northbridge_init(void)
/* Disable LaGrande Technology (LT) */
read32((void *)TPM_BASE_ADDRESS);
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
}