Rename ECAM-specific MMCONF Kconfigs

Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/amd/picasso/Kconfig

@@ -200,10 +200,10 @@ config RAMBASE
 	hex
 	default 0x10000000
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xF8000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	default 64
 
 config VERSTAGE_ADDR

src/soc/amd/picasso/acpi/sb_pci0_fch.asl

@@ -73,14 +73,14 @@ Method(_CRS, 0) {
 
 	/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
 	MM1B = TOM1
-	Local0 = CONFIG_MMCONF_BASE_ADDRESS
+	Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
 	Local0 -= TOM1
 	MM1L = Local0
 
 	CreateWordField(CRES, ^PSB0._MAX, BMAX)
 	CreateWordField(CRES, ^PSB0._LEN, BLEN)
-	BMAX = CONFIG_MMCONF_BUS_NUMBER - 1
-	BLEN = CONFIG_MMCONF_BUS_NUMBER
+	BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
+	BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
 
 	Return(CRES) /* note to change the Name buffer */
 } /* end of Method(_SB.PCI0._CRS) */

src/soc/amd/picasso/fsp_m_params.c

@@ -19,7 +19,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
 
-	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
+	mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 	mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
 	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);