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sb800: sata combine mode configure fix

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Using micro CIMX_OPTION_ENABLED/CIMX_OPTION_DISABLED to
configure SataIdeCombinedMode is wrong.

sbPowerOnInit() use SataIdeCombinedMode to determine whether hide the IDE controller
  0: IDE controller is exposed and Combined Mode is enabled.
     SATA controller has control over Port0 through Port3,
     IDE controller has control over Port4 and Port5
  1: IDE controller is hidden and Combined Mode is disabled,
     SATA controller has full control of all 6 Ports when operating in non-IDE mode

Change-Id: I32e7101737f1dbfff49daa58670e6820b476b250
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/229
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh 2011-10-10 18:23:49 +08:00 committed by Marc Jones
parent 1386fa747d
commit 4e9c4c8cc2
2 changed files with 12 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/vendorcode/amd/cimx/sb800/SATA.c
View File

@ -470,7 +470,7 @@ sataInitAfterPciEnum (
if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {
// RIAD or AHCI // RIAD or AHCI
if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
// RPR 8.10 Disabling CCC (Command Completion Coalescing) support. // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.
@ -631,7 +631,7 @@ sataInitLatePost (
//Enable write access to pci header, pm capabilities //Enable write access to pci header, pm capabilities
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { // if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);
// } // }
sataBar5setting (pConfig, &ddBar5); sataBar5setting (pConfig, &ddBar5);

10
src/vendorcode/amd/cimx/sb800/SBTYPE.h
View File

@ -1106,6 +1106,16 @@ typedef unsigned int CIM_STATUS;
*/ */
#define CIMX_OPTION_ENABLED 1 #define CIMX_OPTION_ENABLED 1
/**
* SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode
*/
#define SATA_IDE_COMBINE_ENABLE 0
/**
* SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode
*/
#define SATA_IDE_COMBINE_DISABLE 1
// mov al, code // mov al, code
// out 80h, al // out 80h, al
// jmp $ // jmp $