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soc/intel/alderlake: Update chipset.cb for TCSS and USB

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Follow TGL chipset.cb to add alias for TCSS and USB ports.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Eric Lai
2020-12-21 16:57:49 +08:00
committed by Tim Wawrzynczak
parent bd0fa62b6b
commit 4ea47c32b0
2 changed files with 96 additions and 6 deletions
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4
src/soc/intel/alderlake/Kconfig
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@@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION
select DRIVERS_USB_ACPI
select FSP_COMPRESS_FSP_S_LZ4
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_M_XIP
@@ -52,6 +53,9 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_USB4
select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET