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soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports

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USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is
implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI
USB2 port reset event issued by the xHCI driver shall trigger a message
upstream to CPU to wake it from the low power state which allows a USB3
device that downgraded to USB2 to upgrade back to USB3.

BUG=b:176575892
TEST=Built and booted to kernel on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao
2021-01-01 14:19:36 -08:00
committed by Patrick Georgi
parent 81a4c344e7
commit 4ead6b3367
2 changed files with 5 additions and 0 deletions
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3
src/soc/intel/tigerlake/fsp_params.c
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@ -159,6 +159,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
else
params->Usb2OverCurrentPin[i] = 0xff;
if (config->usb2_ports[i].type_c)
params->PortResetMessageEnable[i] = 1;
}
for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {