soc/intel: Use of common reset code block

This patch removes all redundant reset code block from each SoC
and make use of common reset code block(fsp_reset.c) based on
SOC_INTEL_COMMON_FSP_RESET.

Respective SoC Kconfig to choose correct FSP global reset type as
per FSP integration guide.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/skylake/Kconfig

@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_SUPPORTS_PM_TIMER_EMULATION
 	select FSP_M_XIP
+	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
 	select HAVE_FSP_LOGO_SUPPORT
@@ -63,6 +64,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_THERMAL
 	select SOC_INTEL_COMMON_BLOCK_UART
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
+	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_PCH_BASE
 	select SOC_INTEL_COMMON_NHLT
 	select SOC_INTEL_COMMON_RESET

src/soc/intel/skylake/reset.c

@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <cf9_reset.h>
-#include <console/console.h>
-#include <fsp/util.h>
 #include <intelblocks/pmclib.h>
 #include <soc/intel/common/reset.h>
 #include <soc/me.h>
@@ -30,17 +28,3 @@ void do_global_reset(void)
 		do_force_global_reset();
 	}
 }
-
-void chipset_handle_reset(uint32_t status)
-{
-	switch (status) {
-	case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
-		printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
-		global_reset();
-		break;
-	default:
-		printk(BIOS_ERR, "unhandled reset type %x\n", status);
-		die("unknown reset type");
-		break;
-	}
-}