broadwell: Change all SoC headers to <soc/headername.h> system

This patch aligns broadwell to the new SoC header include scheme.

BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.

Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/mainboard/google/samus/acpi_tables.c

@@ -29,8 +29,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
-#include <broadwell/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
 #include "thermal.h"
 
 void acpi_create_gnvs(global_nvs_t *gnvs)

src/mainboard/google/samus/chromeos.c

@@ -26,7 +26,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 
 /* SPI Write protect is GPIO 16 */

src/mainboard/google/samus/fadt.c

@@ -19,7 +19,7 @@
  */
 
 #include <string.h>
-#include <broadwell/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/google/samus/gpio.h

@@ -20,7 +20,7 @@
 #ifndef SAMUS_GPIO_H
 #define SAMUS_GPIO_H
 
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 #define SAMUS_GPIO_PP3300_AUTOBAHN_EN	23
 #define SAMUS_GPIO_SSD_RESET_L		47

src/mainboard/google/samus/pei_data.c

@@ -19,9 +19,9 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {

src/mainboard/google/samus/romstage.c

@@ -22,12 +22,12 @@
 #include <console/console.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>
-#include <broadwell/cpu.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/pm.h>
-#include <broadwell/romstage.h>
+#include <soc/cpu.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
 #include <mainboard/google/samus/spd/spd.h>
 #include <mainboard/google/samus/gpio.h>
 

src/mainboard/google/samus/smihandler.c

@@ -21,15 +21,15 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
 #include <elog.h>
 #include <ec/google/chromeec/ec.h>
-#include <broadwell/gpio.h>
-#include <broadwell/iomap.h>
-#include <broadwell/nvs.h>
-#include <broadwell/pm.h>
-#include <broadwell/smm.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
 #include "ec.h"
 #include "gpio.h"
 

src/mainboard/google/samus/spd/spd.c

@@ -21,9 +21,9 @@
 #include <cbfs.h>
 #include <console/console.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/romstage.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <mainboard/google/samus/ec.h>
 #include <mainboard/google/samus/gpio.h>

src/mainboard/intel/wtm2/acpi_tables.c

@@ -29,8 +29,8 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/cpu.h>
-#include <broadwell/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
 #include "thermal.h"
 
 void acpi_create_gnvs(global_nvs_t *gnvs)

src/mainboard/intel/wtm2/chromeos.c

@@ -22,7 +22,7 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 /* Compile-time settings for developer and recovery mode. */
 #define DEV_MODE_SETTING 1

src/mainboard/intel/wtm2/fadt.c

@@ -18,7 +18,7 @@
  */
 
 #include <string.h>
-#include <broadwell/acpi.h>
+#include <soc/acpi.h>
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {

src/mainboard/intel/wtm2/gpio.h

@@ -20,7 +20,7 @@
 #ifndef INTEL_WTM2_GPIO_H
 #define INTEL_WTM2_GPIO_H
 
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
 
 static const struct gpio_config mainboard_gpio_config[] = {
 	PCH_GPIO_NATIVE,        /* 0: LPSS_UART1_RXD */

src/mainboard/intel/wtm2/mainboard_smi.c

@@ -20,8 +20,8 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <broadwell/nvs.h>
-#include <broadwell/smm.h>
+#include <soc/nvs.h>
+#include <soc/smm.h>
 
 int mainboard_io_trap_handler(int smif)
 {

src/mainboard/intel/wtm2/pei_data.c

@@ -20,9 +20,9 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {

src/mainboard/intel/wtm2/romstage.c

@@ -21,10 +21,10 @@
 #include <console/console.h>
 #include <stdint.h>
 #include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/romstage.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
 #include "gpio.h"
 
 void mainboard_romstage_entry(struct romstage_params *rp)