mb/google/brya/var/xol: Update NVMe clock source index to 0

Change ClkSrc index for NVME to 0 from 1 by referring to proto2
schematics.

BUG=b:326481458
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage

Change-Id: I7ea1cd7d8e16d4cee953e931d2f1829eae7d1978
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80768
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/mainboard/google/brya/variants/xol/overridetree.cb

@@ -261,10 +261,10 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref pcie4_0 on
-		# Enable CPU PCIE RP 1 using CLK 1
+		# Enable CPU PCIE RP 1 using CLK 0
 			register "cpu_pcie_rp[CPU_RP(1)]" = "{
 				.clk_req = 1,
-				.clk_src = 1,
+				.clk_src = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			probe STORAGE STORAGE_NVME