arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE

If stage cache is enabled, we should not allow S3 resume
to load firmware from non-volatile memory.

This also adds board reset for failing to load postcar
from stage cache.

Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/haswell/Kconfig

@@ -35,16 +35,4 @@ config IED_REGION_SIZE
 config SMM_RESERVED_SIZE
 	hex
 	default 0x100000
-
-config RESET_ON_INVALID_RAMSTAGE_CACHE
-	bool "Reset the system on S3 wake when ramstage cache invalid."
-	default n
-	help
-	  The haswell romstage code caches the loaded ramstage program
-	  in SMM space. On S3 wake the romstage will copy over a fresh
-	  ramstage that was cached in the SMM space. This option determines
-	  the action to take when the ramstage cache is invalid. If selected
-	  the system will reset otherwise the ramstage will be reloaded from
-	  cbfs.
-
 endif