fixup. SMP works fine.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -12,6 +12,7 @@ uses CONFIG_COMPRESS
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uses CONFIG_IOAPIC
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uses CONFIG_ROM_STREAM
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uses CONFIG_ROM_STREAM_START
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uses CONFIG_SMP
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uses CONFIG_UDELAY_TSC
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uses CPU_FIXUP
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uses ENABLE_FIXED_AND_VARIABLE_MTRRS
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@@ -23,8 +24,8 @@ uses HAVE_PIRQ_TABLE
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uses i586
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uses i686
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uses INTEL_PPRO_MTRR
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uses HEAP_SIZE
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uses IRQ_SLOT_COUNT
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uses HEAP_SIZE
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uses k7
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uses k8
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uses MAINBOARD_PART_NUMBER
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@@ -54,8 +55,8 @@ uses CONFIG_CHIP_CONFIGURE
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option CONFIG_CHIP_CONFIGURE=1
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option MAXIMUM_CONSOLE_LOGLEVEL=7
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option DEFAULT_CONSOLE_LOGLEVEL=7
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option MAXIMUM_CONSOLE_LOGLEVEL=9
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option DEFAULT_CONSOLE_LOGLEVEL=9
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option CONFIG_CONSOLE_SERIAL8250=1
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option HAVE_OPTION_TABLE=1
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@@ -78,14 +79,14 @@ option SIO_SYSTEM_CLK_INPUT=0
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### Build code to export a programmable irq routing table
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###
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=7
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option IRQ_SLOT_COUNT=18
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#
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###
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### Build code for SMP support
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### Only worry about 2 micro processors
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###
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##option CONFIG_SMP=1
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option MAX_CPUS=1
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option CONFIG_SMP=1
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option MAX_CPUS=2
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#
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###
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### Build code to setup a generic IOAPIC
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@@ -111,13 +112,7 @@ option MEMORY_HOLE=0
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### processor identification
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###
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option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
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#
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###
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### Clean up the motherboard id strings
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###
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#option MAINBOARD_PART_NUMBER="Solo7"
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#option MAINBOARD_VENDOR="AMD"
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#
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###
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### Call the final_mainboard_fixup function
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###
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@@ -151,7 +146,7 @@ option CONFIG_COMPRESS=1
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option USE_ELF_BOOT=1
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## LinuxBIOS C code runs at this location in RAM
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option _RAMBASE=0x00100000
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option _RAMBASE=0x4000
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##
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## Use a 64K stack
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@@ -195,7 +190,8 @@ romimage "fallback"
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option CONFIG_ROM_STREAM = 1
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option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
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mainboard arima/hdama
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payload ../../../../opteron_phase1
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payload ../../../../tg3--ide_disk.zelf
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# payload ../../../../opteron_phase1
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end
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buildrom ROM_SIZE "normal" "fallback"
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