mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held
2021-05-31 19:44:46 +02:00
parent c4eb45fa85
commit 4fbab545b2
7 changed files with 33 additions and 33 deletions

View File

@@ -37,7 +37,7 @@ chip soc/amd/picasso
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 1.7 on end # GPP Bridge 6 - NVME
device ref gpp_bridge_6 on end # NVME
end # domain
device mmio 0xfedc4000 on end