soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
Do it in coreboot code instead of letting FSP do it. Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
committed by
Patrick Georgi
parent
941796a50d
commit
4ff63d3a11
@ -391,17 +391,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* Set TccActivationOffset */
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tconfig->TccActivationOffset = config->tcc_offset;
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/* Already handled in coreboot code, so tell FSP to ignore UPDs */
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params->PchIoApicBdfValid = 0;
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/* Enable VT-d and X2APIC */
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if (!config->ignore_vtd && soc_is_vtd_capable()) {
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params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
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params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
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params->X2ApicOptOut = 0;
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tconfig->VtdDisable = 0;
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params->PchIoApicBdfValid = 1;
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params->PchIoApicBusNumber = V_P2SB_IBDF_BUS;
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params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV;
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params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN;
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}
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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