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Unify use of post_code

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Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>                                                                                                         
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Alexandru Gagniuc
2011-04-11 20:17:22 +00:00
committed by Stefan Reinauer
parent 1fa61ebb33
commit 5005bb06c1
40 changed files with 408 additions and 262 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/amd/model_gx2/cache_as_ram.inc
View File

@ -27,6 +27,7 @@
#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
#include <cpu/amd/gx2def.h>
#include <cpu/x86/post_code.h>
/***************************************************************************
/**
/** DCacheSetup
@ -184,7 +185,7 @@ done_cache_as_ram_main:
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
/* TODO For suspend/resume the cache will have to live between
* CONFIG_RAMBASE and CONFIG_RAMTOP
@ -201,7 +202,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/amd/model_lx/cache_as_ram.inc
View File

@ -26,6 +26,7 @@
#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
#include <cpu/amd/lxdef.h>
#include <cpu/x86/post_code.h>
/***************************************************************************
/**
/** DCacheSetup
@ -210,7 +211,7 @@ done_cache_as_ram_main:
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
/* TODO For suspend/resume the cache will have to live between
* CONFIG_RAMBASE and CONFIG_RAMTOP
@ -227,7 +228,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

6
src/cpu/amd/sc520/raminit.c
View File

@ -144,13 +144,13 @@ void setupsc520(void)
/* the 0x80 led should now be working*/
outb(0xaa, 0x80);
post_code(0xaa);
#if 0
/* wtf are 680 leds ... */
/* wtf are 680 leds ... *//* <-- WTF is this comment? */
par = (unsigned long *) 0xfffef0c4;
*par = 0x28000680;
/* well? */
outb(0x55, 0x80);
post_code(0x55);
#endif
/* set the uart baud rate clocks to the normal 1.8432 MHz.*/

5
src/cpu/intel/car/cache_as_ram.inc
View File

@ -24,6 +24,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/x86/post_code.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
@ -364,7 +365,7 @@ lout:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -375,7 +376,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/intel/model_106cx/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@ -229,7 +230,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -240,7 +241,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/intel/model_6fx/cache_as_ram.inc
View File

@ -20,6 +20,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/post_code.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@ -243,7 +244,7 @@ clear_mtrrs:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -254,7 +255,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

5
src/cpu/via/car/cache_as_ram.inc
View File

@ -27,6 +27,7 @@
#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
#include <console/post_codes.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
@ -261,7 +262,7 @@ testok:
/* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
post_code(0x11)
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl %ebp, %esi
@ -272,7 +273,7 @@ __main:
call copy_and_run
.Lhlt:
post_code(0xee)
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

3
src/cpu/x86/32bit/entry32.inc
View File

@ -1,6 +1,7 @@
/* For starting coreboot in protected mode */
#include <arch/rom_segs.h>
#include <cpu/x86/post_code.h>
.code32
@ -51,7 +52,7 @@ __protected_start:
/* Save the BIST value */
movl %eax, %ebp
post_code(0x10)
post_code(POST_ENTER_PROTECTED_MODE)
movw $ROM_DATA_SEG, %ax
movw %ax, %ds