Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Stefan Reinauer
parent
1fa61ebb33
commit
5005bb06c1
@@ -27,6 +27,7 @@
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#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
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#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
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#include <cpu/amd/gx2def.h>
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#include <cpu/x86/post_code.h>
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/***************************************************************************
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/**
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/** DCacheSetup
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@@ -184,7 +185,7 @@ done_cache_as_ram_main:
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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post_code(0x11)
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post_code(POST_PREPARE_RAMSTAGE)
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/* TODO For suspend/resume the cache will have to live between
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* CONFIG_RAMBASE and CONFIG_RAMTOP
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@@ -201,7 +202,7 @@ __main:
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call copy_and_run
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.Lhlt:
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post_code(0xee)
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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@@ -26,6 +26,7 @@
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#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
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#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
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#include <cpu/amd/lxdef.h>
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#include <cpu/x86/post_code.h>
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/***************************************************************************
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/**
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/** DCacheSetup
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@@ -210,7 +211,7 @@ done_cache_as_ram_main:
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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post_code(0x11)
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post_code(POST_PREPARE_RAMSTAGE)
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/* TODO For suspend/resume the cache will have to live between
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* CONFIG_RAMBASE and CONFIG_RAMTOP
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@@ -227,7 +228,7 @@ __main:
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call copy_and_run
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.Lhlt:
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post_code(0xee)
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post_code(POST_DEAD_CODE)
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hlt
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jmp .Lhlt
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@@ -144,13 +144,13 @@ void setupsc520(void)
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/* the 0x80 led should now be working*/
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outb(0xaa, 0x80);
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post_code(0xaa);
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#if 0
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/* wtf are 680 leds ... */
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/* wtf are 680 leds ... *//* <-- WTF is this comment? */
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par = (unsigned long *) 0xfffef0c4;
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*par = 0x28000680;
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/* well? */
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outb(0x55, 0x80);
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post_code(0x55);
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#endif
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/* set the uart baud rate clocks to the normal 1.8432 MHz.*/
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