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soc/intel/skylake/chip.h: Provide some enums

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Provide some enums instead of unreadable comments that are usually
copied all over.

Change-Id: Iff551565647f28ecb226e1df633b4deec0ab0a7f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Nico Huber
2017-05-09 16:11:27 +02:00
committed by Stefan Reinauer
parent e7947df462
commit 503965f939
1 changed files with 53 additions and 35 deletions
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88
src/soc/intel/skylake/chip.h
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@@ -302,26 +302,38 @@ struct soc_intel_skylake_config {
* 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn * 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn
*/ */
u8 PmConfigDeepSxPol; u8 PmConfigDeepSxPol;
/*
* SLP_S3 Minimum Assertion Width Policy. Values 0: PchSlpS360us, enum {
* 1: PchSlpS31ms, 2: PchSlpS350ms, 3: PchSlpS32s. SLP_S3_MIN_ASSERT_60US = 0,
*/ SLP_S3_MIN_ASSERT_1MS = 1,
u8 PmConfigSlpS3MinAssert; SLP_S3_MIN_ASSERT_50MS = 2,
/* SLP_S3_MIN_ASSERT_2S = 3,
* SLP_S4 Minimum Assertion Width Policy. Values 0: PchSlpS4PchTime, } PmConfigSlpS3MinAssert;
* 1: PchSlpS41s, 2: PchSlpS42s, 3: PchSlpS43s, 4: PchSlpS44s.
*/ enum {
u8 PmConfigSlpS4MinAssert; SLP_S4_MIN_ASSERT_PCH = 0,
/* SLP_S4_MIN_ASSERT_1S = 1,
* SLP_SUS Minimum Assertion Width Policy. Values 0: PchSlpSus0ms, SLP_S4_MIN_ASSERT_2S = 2,
* 1: PchSlpSus500ms, 2: PchSlpSus1s, 3: PchSlpSus4s. SLP_S4_MIN_ASSERT_3S = 3,
*/ SLP_S4_MIN_ASSERT_4S = 4,
u8 PmConfigSlpSusMinAssert; } PmConfigSlpS4MinAssert;
/*
* SLP_A Minimum Assertion Width Policy. Values 0: PchSlpA0ms, /* When deep Sx enabled: Must be greater than or equal to
* 1: PchSlpA4s, 2: PchSlpA98ms, 3: PchSlpA2s. all other minimum assertion widths. */
*/ enum {
u8 PmConfigSlpAMinAssert; SLP_SUS_MIN_ASSERT_0MS = 0,
SLP_SUS_MIN_ASSERT_500MS = 1,
SLP_SUS_MIN_ASSERT_1S = 2,
SLP_SUS_MIN_ASSERT_4S = 3,
} PmConfigSlpSusMinAssert;
enum {
SLP_A_MIN_ASSERT_0MS = 0,
SLP_A_MIN_ASSERT_4S = 1,
SLP_A_MIN_ASSERT_98MS = 2,
SLP_A_MIN_ASSERT_2S = 3,
} PmConfigSlpAMinAssert;
/* /*
* This member describes whether or not the PCI ClockRun feature of PCH * This member describes whether or not the PCI ClockRun feature of PCH
* should be enabled. Values 0: Disabled, 1: Enabled * should be enabled. Values 0: Disabled, 1: Enabled
@@ -345,24 +357,30 @@ struct soc_intel_skylake_config {
*/ */
u8 PchPmSlpS0VmEnable; u8 PchPmSlpS0VmEnable;
/* enum {
* Reset Power Cycle Duration could be customized in the unit of second. RESET_POWER_CYCLE_DEFAULT = 0,
* PCH HW default is 4 seconds, and range is 1~4 seconds. RESET_POWER_CYCLE_1S = 1,
* Values: 0x0 - 0s, 0x1 - 1s, 0x2 - 2s, 0x3 - 3s, 0x4 - 4s RESET_POWER_CYCLE_2S = 2,
*/ RESET_POWER_CYCLE_3S = 3,
u8 PmConfigPwrCycDur; RESET_POWER_CYCLE_4S = 4,
} PmConfigPwrCycDur;
/* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/ /* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
u8 SerialIrqConfigSirqEnable; u8 SerialIrqConfigSirqEnable;
/* Serial IRQ Mode Select. Values: 0: PchQuietMode,
* 1: PchContinuousMode. enum {
*/ SERIAL_IRQ_QUIET_MODE = 0,
u8 SerialIrqConfigSirqMode; SERIAL_IRQ_CONTINUOUS_MODE = 1,
/* } SerialIrqConfigSirqMode;
* Start Frame Pulse Width.
* Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2; PchSfpw8Clk. enum {
*/ SERIAL_IRQ_FRAME_PULSE_4CLK = 0,
u8 SerialIrqConfigStartFramePulse; SERIAL_IRQ_FRAME_PULSE_6CLK = 1,
SERIAL_IRQ_FRAME_PULSE_8CLK = 2,
} SerialIrqConfigStartFramePulse;
u8 FspSkipMpInit; u8 FspSkipMpInit;
/* /*
* VrConfig Settings for 5 domains * VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring, * 0 = System Agent, 1 = IA Core, 2 = Ring,