Remove DEFAULT_PCIEXBAR alias

The other DEFAULT_ entries are just immediate
constants.

Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/denverton_ns/acpi/northcluster.asl

@@ -138,7 +138,7 @@ Device (PDRC)
 
 	Name (PDRS, ResourceTemplate() {
 		// PCIEXBAR memory range
-		Memory32Fixed(ReadOnly, DEFAULT_PCIEXBAR, 0x10000000)
+		Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
 		// TSEG
 		Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
 	})

src/soc/intel/denverton_ns/include/soc/iomap.h

@@ -23,7 +23,6 @@
  */
 
 /* Northbridge BARs */
-#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
 #define DEFAULT_MCHBAR 0xfed10000		    /* 16 KB */
 
 /* Southbridge internal device IO BARs (Set to match FSP settings) */