trivial warning fixes, mostly for ACPI code
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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committed by
Stefan Reinauer
parent
dfd29aa413
commit
50776fab1c
@@ -73,12 +73,12 @@ unsigned pm_base;
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static void acpi_init(struct device *dev)
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{
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uint8_t byte;
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uint16_t word;
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uint16_t pm10_bar;
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uint32_t dword;
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int on;
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#if 0
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uint16_t word;
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printk_debug("ACPI: disabling NMI watchdog.. ");
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byte = pci_read_config8(dev, 0x49);
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pci_write_config8(dev, 0x49, byte | (1<<2));
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@@ -98,9 +98,8 @@ static void acpi_init(struct device *dev)
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word = pci_read_config16(dev, 0x46);
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pci_write_config16(dev, 0x46, word | (1<<9));
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printk_debug("done.\n");
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#endif
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/* To enable the register 0xcf9 in the IO space
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* bit [D5] is set in the amd8111 configuration register.
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* The config. reg. is devBx41. Register 0xcf9 allows
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@@ -54,12 +54,12 @@ static void nic_init(struct device *dev)
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/* Hard Reset PHY */
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printk_debug("Reseting PHY... ");
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if (conf->phy_lowreset) {
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write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
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write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY);
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} else {
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write32((void *)(mmio + CMD3), VAL0 | RESET_PHY);
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write32((mmio + CMD3), VAL0 | RESET_PHY);
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}
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mdelay(15);
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write32((void *)(mmio + CMD3), RESET_PHY);
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write32((mmio + CMD3), RESET_PHY);
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printk_debug("Done\n");
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}
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