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mb/system76/tgl-u: Remove CPU PCIe RP RTD3 config

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This has caused nothing but issues trying to get different drives to
behave correctly. Just remove it.

Change-Id: I72216960f9445e357b9c51faf3735f232adec78c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-10-26 09:52:53 -06:00
committed by Tim Crawford
parent ca16834a9b
commit 509a5160a6
3 changed files with 0 additions and 18 deletions
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6
src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
View File

@@ -21,12 +21,6 @@ chip soc/intel/tigerlake
# PCIe PEG0 x4, Clock 0 (SSD1) # PCIe PEG0 x4, Clock 0 (SSD1)
register "PcieClkSrcUsage[0]" = "0x40" register "PcieClkSrcUsage[0]" = "0x40"
register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[0]" = "0"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" # SSD1_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" # GPP_D13_SSD1_PLT_RST#
register "srcclk_pin" = "0" # SSD1_CLKREQ#
device generic 0 on end
end
end end
device ref north_xhci on # J_TYPEC2 device ref north_xhci on # J_TYPEC2
register "UsbTcPortEn" = "1" register "UsbTcPortEn" = "1"

6
src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
View File

@@ -21,12 +21,6 @@ chip soc/intel/tigerlake
# PCIe PEG0 x4, Clock 0 (SSD1) # PCIe PEG0 x4, Clock 0 (SSD1)
register "PcieClkSrcUsage[0]" = "0x40" register "PcieClkSrcUsage[0]" = "0x40"
register "PcieClkSrcClkReq[0]" = "0" register "PcieClkSrcClkReq[0]" = "0"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3
register "srcclk_pin" = "0" # SSD1_CLKREQ#
device generic 0 on end
end
end end
device ref north_xhci on # J_TYPEC2 device ref north_xhci on # J_TYPEC2
register "UsbTcPortEn" = "1" register "UsbTcPortEn" = "1"

6
src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
View File

@@ -22,12 +22,6 @@ chip soc/intel/tigerlake
# Despite the name, SSD2_CLKREQ# is used for SSD1 # Despite the name, SSD2_CLKREQ# is used for SSD1
register "PcieClkSrcUsage[3]" = "0x40" register "PcieClkSrcUsage[3]" = "0x40"
register "PcieClkSrcClkReq[3]" = "3" register "PcieClkSrcClkReq[3]" = "3"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
register "srcclk_pin" = "3" # SSD2_CLKREQ#
device generic 0 on end
end
end end
device ref north_xhci on # J_TYPEC1 device ref north_xhci on # J_TYPEC1
register "UsbTcPortEn" = "1" register "UsbTcPortEn" = "1"